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as4c 32 m16d2 alliance memory inc . 551 taylor way, san carlos, ca 94070 tel : (650) 610- 6800 fax : (650) 620- 9211 alliance memory inc. reserves the right to change products or specification without notice. 1 rev. 1.1 feb. /2013 512m ( 32 m x 16 bit) ddrii synchronous dram (sdram) confidential advanced (rev. 1. 1, feb. / 20 13) features ? jedec standard compliant ? ? dd & v ddq = +1.8v ? 0.1v ? ? ? ? ? ? ? ? ? ? ? ? ck ? b urst lengths: 4 or 8 ? ? ? ? ? ? ? 85c) - industrial (-40 ~ 95c) ? 7.8s @ 0 Q tc Q +85 3.9s @ +85 tc Q +95 ? 84- ball 8x12.5x1.2mm (max) fbga - pb and halogen free overview the AS4C32M16D2 ddr2 sdram is a high-speed cmos double-data-rate- two (ddr 2) , synchronous dynamic random-access memory (sdram) containing 512 mbits in a 16-bit wide data i/os. it is internally configured as a quad bank dram, 4 banks x 8mb addresses x 16 i/os the device is designed to comply with ddr2 dram key features such as posted cas# with additive latency, write latency = read latency -1, off-chip driver (ocd) impedance adjustment, and on die termination(odt) . all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. inputs are latched at the cross point of differential clocks (ck rising and ck# falling) all i/os are synchronized with a pair of bidirectional strobes (dqs and dqs#) in a source synchronous fashion. the address bus is used to convey row, column, and bank address information in ras # , cas# multiplexing style. accesses begin with the registration of a bank activate command, and then it is followed by a read or write command. read and write accesses to the ddr2 sdram are 4 or 8-bit burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. operating the four memory banks in an interleaved fashion allows random access operation to occur at a higher rate than is possible with standard drams. an auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. a sequential and gapless data rate is possible depending on burst length, cas latency, and speed grade of the device. ordering information part number clock frequency data rate packag e temperature temp range AS4C32M16D2 - 25 b c n 400 mhz 800mbps/pin 84 - ball fbga commercial -0 ~ 85c AS4C32M16D2 - 25 bin 400 mhz 800mb p s/pin 84 - ball fbga industrial -4 0 ~ 95c b: indicates 84-ball (8.0 x 12.5 x 1.2mm) tfbga package c: indicates commercial temp. i: indicates industrial temp. n: indicates pb and halogen free rohs
as4c32m16d 2 alliance memory in c . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 2 rev. 1. 1 feb . /201 3 figure 1. ball assignment (fbga top view) a b c d e 1 2 3 7 8 9 v d d n c d q 1 4 v s s q v d d q d q 9 d q 1 2 v s s q v d d n c v s s u d m v d d q d q 1 1 v s s . v s s q u d q s # u d q s v s s q v d d q d q 8 d q 1 0 v s s q v s s q l d q s # v d d q d q 1 5 v d d q d q 1 3 v d d q f d q 6 v s s q l d m l d q s v s s q d q 7 g v d d q d q 1 v d d q v d d q d q 0 v d d q h d q 4 v s s q d q 3 d q 2 v s s q d q 5 j v d d l v r e f v s s v s s d l c k v d d k c k e w e # r a s # c k # o d t l n c b a 0 b a 1 c a s # c s # m a 1 0 a 1 a 2 a 0 v d d n v s s a 3 a 5 a 6 a 4 p a 7 a 9 a 1 1 a 8 v s s r v d d a 1 2 n c n c n c
as4c32m16d 2 alliance memory in c . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 3 rev. 1. 1 feb . /201 3 figure 2 . block diagram c k # c k e c s # r a s # c a s # w e # d l l c l o c k b u f f e r c o m m a n d d e c o d e r c o l u m n c o u n t e r c o n t r o l s i g n a l g e n e r a t o r a d d r e s s b u f f e r r e f r e s h c o u n t e r 8 m x 1 6 c e l l a r r a y ( b a n k # 0 ) r o w d e c o d e r 8 m x 1 6 c e l l a r r a y ( b a n k # 1 ) r o w d e c o d e r 8 m x 1 6 c e l l a r r a y ( b a n k # 2 ) r o w d e c o d e r 8 m x 1 6 c e l l a r r a y ( b a n k # 3 ) r o w d e c o d e r c o l u m n d e c o d e r c o l u m n d e c o d e r c o l u m n d e c o d e r c o l u m n d e c o d e r m o d e r e g i s t e r a 1 0 / a p a 9 a 1 1 a 1 2 b a 0 b a 1 a 0 c k d a t a s t r o b e b u f f e r l d q s l d q s # u d q s u d q s # d q b u f f e r l d m u d m d q 1 5 d q 0 ~ o d t ~
as4c32m16d 2 alliance memory in c . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 4 rev. 1. 1 feb . /201 3 figure 3. state diagram ( e ) m r s s e t t i n g m r , e m r ( 1 ) e m r ( 2 ) e m r ( 3 ) o c d c a l i b r a t i o n i n i t i a l i z a t i o n s e q u e n c e i d l e a l l b a n k s p r e c h a r g e d s e l f r e f r e s h i n g r e f r e s h i n g p r e c h a r g e p o w e r d o w n a c t i v a t i n g a c t i v e p o w e r d o w n b a n k a c t i v e w r i t i n g w r i t i n g w i t h a u t o p r e c h a r g e p r e c h a r g i n g r e a d i n g w i t h a u t o p r e c h a r g e r e a d i n g a c t c k e l c k e h c k e l w r r d a r d a w r a w r a w r r d r d p r , p r a p r , p r a p r , p r a r d a w r a c k e l c k e h c k e l s r f c k e h r e f c k e l w r r d p r c k e l c k e l a u t o m a t i c s e q u e n c e c a m m a n d s e q u e n c e c k e l = c k e l o w , e n t e r p o w e r d o w n c k e h = c k e h i g h , e x i t p o w e r d o w n , e x i t s e l f r e f r e s h a c t = a c t i v a t e w r ( a ) = w r i t e ( w i t h a u t o p r e c h a r g e ) r d ( a ) = r e a d ( w i t h a u t o p r e c h a r g e ) p r ( a ) = p r e c h a r g e ( a l l ) ( e ) m r s = ( e x t e n d e d ) m o d e r e g i s t e r s e t s r f = e n t e r s e l f r e f r e s h r e f = r e f r e s h n o t e : u s e c a u t i o n w i t h t h i s d i a g r a m . i t i s i n d e n t e d t o p r o v i d e a f l o o r p l a n o f t h e p o s s i b l e s t a t e t r a n s i t i o n s a n d t h e c o m m a n d s t o c o n t r o l t h e m , n o t a l l d e t a i l s . i n p a r t i c u l a r s i t u a t i o n s i n v o l v i n g m o r e t h a n o n e b a n k , e n a b l i n g / d i s a b l i n g o n - d i e t e r m i n a t i o n , p o w e r d o w n e n t r y / e x i t , t i m i n g r e s t r i c t i o n s d u r i n g s t a t e t r a n s i t i o n s , a m o n g o t h e r t h i n g s , a r e n o t c a p t u r e d i n f u l l d e t a i l .
as4c32m16d 2 alliance memory in c . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 5 rev. 1. 1 feb . /201 3 ball descriptions table 3 . ball descriptions symbol type description ck, ck # input differential clock: ck, ck # are driven by the system clock. all sdram input signals are sampled on the crossing of po sitive edge of ck and negative edge of ck#. output ( r ead) data is referenced to the crossings of ck and ck# (both directions of crossing). cke input clock enable: cke activates ( high) and deactivates ( low ) the ck signal. if cke goes low synchronously with clock, the internal clock is suspended from the next clock cycle and the state of output and burst address is froze n as long as the cke remains low . when all banks are in the id le state, deactivating the clock controls the entry to the power down and self refresh modes. b a 0, b a 1 input bank address : b a 0 and b a 1 define to which bank the bankactivate, read, write, or bankprecharge command is being applied. a0 - a1 2 input address inp uts: a0 - a1 2 are sampled during the bankactivate command (row address a0 - a1 2 ) and read/write command (column address a0 - a 9 with a10 defining auto precharge ). cs # input chip select: cs # enables (sampled low) and disables (sampled high) the command decoder . all commands are masked when cs # is sampled high. cs # provides for external bank selection on systems with multiple banks. it is considered part of the command code. ras # input row address strobe: the ras # signal defines the operation co mmands in conjunct ion with the cas # and we # signals and is latched at the crossing of positive edges of ck and negative edge of ck#. when ras# and cs # are asserted "low" and cas # is asserted "high," either the bankactivate command or the precha rge command is selected by the we # signal. when the we # is asserted "high," the bankactivate command is selected and the bank designated by ba is turned on to the active state. when the we # is asserted "low," the precharge command is selected and the bank designated by b a is switched t o the idle state after the precharge operation. cas # input column address strobe: the cas # signal defines the operation commands in conjunction with the ras# and we # signals and is latched at the crossing of positive edges of ck and negative edge of ck# . when ras # is held "high" and cs # is asserted "low," the column access is started by asserting cas # "low." then, the read or write co mmand is selected by asserting we # or low
as4c32m16d 2 alliance memory in c . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 6 rev. 1. 1 feb . /201 3 dq0 - dq15 input / output data i/o: bi - directional data bus. odt input on die termination: odt enables internal termination resistance. i t is applied to each dq, ldqs / ldqs # , udqs / udqs # , ldm, and udm signal. the odt pin is ignored if the emr (1) is programmed to disable odt. v dd supply power supply: + 1.8 v r 0.1v v ss supply ground v dd l supply dll power supply: + 1.8 v r 0.1v v ss d l supply dll ground v ddq supply dq power: + 1.8 v r 0.1v. v ssq supply dq ground v ref supply reference voltage for inputs: +0.5*v ddq nc - no connect: these pins should be left unconnected.
as4c32m16d 2 alliance memory in c . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 7 rev. 1. 1 feb . /201 3 operation mode table 4 shows the truth table for the operation commands. tab le 4 . truth table (note (1), (2 )) command state cke n - 1 cke n dm ba 0,1 a 10 a 0 - 9, 11 - 12 cs# ras# cas# we# bankactivate idle (3) h h x v row address l l h h single bank precharge any h h x v l x l l h l all banks precharge any h h x x h x l l h l write acti ve (3) h h x v l column address (a0 C C
as4c32m16d 2 alliance memory in c . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 8 rev. 1. 1 feb . /201 3 functional description read and write accesses to the ddr2 sdram are burst oriented; accesses start at a selected location and continue for a burst length of four or eight in a programmed sequence. accesses begin with the registration of an active command, which is then followed by a read or write command. the address bits registered coincident with the active command are used to select the ba nk and row to be accessed (ba0, ba1 select the bank; a0 - a12 select the row). the address bits registered coincident with the read or write command are used to select the starting column location for the burst access and to determine if the auto precharge c ommand is to be issued. prior to normal operation, the ddr2 sdram must be initialized. the following sections provide detailed information covering device initialization, register definition, command descriptions, and device operation. ? power - up and initia lization ddr2 sdrams must be powered up and initialized in a predefined manner. operational procedures other than those specified may result in undefined operation. the following sequence is required for power up and initialization. 1. apply power and attem pt to maintain cke below 0.2*v ddq and odt *1 at a low state (all other inputs may be undefined. ) the v dd voltage ramp time must be no greater than 200ms from when v dd ramps from 300mv to v dd min; and during the v dd voltage ramp, |v dd - v ddq | # 0.3 v - v dd , v ddl and v ddq are driven from a single power converter output, and - v tt is limited to 0.95 v max, and - v ref tracks v ddq /2. or - apply v dd before or at the same time as v ddl . - apply v ddl before or at the same time as v ddq . - apply v ddq befo re or at the same time as v tt & v ref . at least one of these two sets of conditions must be met. 2. start clock and maintain stable condition. 3. for the minimum of 200 s after stable power and clock ( ck, ck # ), then apply nop or deselect and take cke high . 4. wait minimum of 400ns then issue precharge all command. nop or deselect applied during 400ns period. 5. issue emrs(2) command. (to issue emrs ( 2) command, provide l ow to ba0, high to ba1.) de high to ba0 and ba1.) 8. issue a mode register set command for dll reset.
as4c32m16d 2 alliance memory in c . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 9 rev. 1. 1 feb . /201 3 ? mode register set(mrs) the mode register stores the data for controlling the va rious operating modes of ddr2 sdram. it controls cas latency, burst length, burst sequence, test mode, dll reset, wr, and various vendor specific options to make ddr2 sdram useful for various applications. the default value of the mode register is not defin ed, therefore the mode register must be programmed during initialization for proper operation. the mode register is written by asserting low on cs#, ras#, cas#, we#, ba0 and ba1, while controlling the state of address pins a0 - a12. the ddr2 sdram should b e in all bank precharge state with cke already high prior to writing into the mode register. the mode register set command cycle time (t mrd ) is required to complete the write operation to the mode register. the mode register contents can be changed using th e same command and clock cycle requirements during normal operation as long as all bank are in the precharge state. the mode register is divided into various fields depending on functionality. - burst length field (a2, a1, a0) this field specifies the data length of column access and selects the burst length. - addressing mode select field (a3) the addressing mode can be interleave mode or sequential mode. both sequential mode and interleave mode support burst length of 4 and 8 . - cas latency field (a6, a5, a4) this field specifies the number of clock cycles from the assertion of the read command to the first read data. the minimum whole value of cas latency depends on the frequency of ck. the minimum whole value satisfying the following formula must be pr ogrammed into this field. t cac (min) # cas latency x t ck - test mode field: a7; dll reset mode field: a8 these two bits must be programmed to "00" in normal operation. - (ba0, ba1) : bank address es to define mrs selection .
as4c32m16d 2 alliance memory in c . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 10 rev. 1. 1 feb . /201 3 table 5. mode register bitmap ba1 ba0 a12 a11 a 10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 address field 0 0 pd wr dll tm cas latency bt burst length mode register a8 dll reset a7 mode a3 burst type a2 a1 a0 bl 0 no 0 normal 0 sequential 0 1 0 4 1 yes 1 test 1 interleave 0 1 1 8 note 1: .for ddr2 - 800, wr (writ e recovery for autoprecharge) min is determined by t ck (avg) max and wr max is determined by t ck (avg) min. wr [cycles] = ru {t wr [ns]/t ck (avg)[ns]}, where ru stands for round up. the mode register must be programmed to this value. this is also used with t rp to determine t dal . ? extended mode register set (emrs ) - emr(1) the extended mode register(1) stores the data for enabling or disabling the dll, output driver strength, odt value selection and additive latency. the default value of the extended mode register is not defined, therefore the extended mode register must be written after power - up for proper operation. the extended mode register is written by asserting low on cs # , ras # , cas # , we # , ba1 and high on ba0, while controlling the states of address pins a0 ~ a12. the ddr2 sdram should be in all bank precharge with cke already high prior to writing into the extended mode register. the mode register set command cycle time (t mrd ) must be satisfied to complete the write operation to the extended mode register. mo de register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in the precharge state. a0 is used for dll enable or disable. a1 is used for enabling a half strength data - output drive r. a3~a5 determine the additive latency, a2 and a6 are used for odt value selection, a7~a9 are used for ocd control, a10 is used for dqs# disable . - dll enable/disable the dll must be enabled for normal operation. dll enable is required during power up initi alization , and upon returning to normal operation after having the dll disabled. the dll is automatically disabled when entering self refresh operation and is automatically re - enabled upon exit of self refresh operation. any time the dll is enabled (and su bsequently reset), 200 clock cycles must occur before a read command can be issued to allow time for the internal clock to be synchronized with the external clock. failing to wait for synchronization to occur may result in a violation of the t ac or t dqsck pa rameters. a12 active power down exit time write recovery for autoprecharge *1 0 fast exit (use t xard ) a11 a10 a9 wr(cycles) a6 a5 a4 cas latency 1 slow exit (use t xards ) 0 0 0 reserved 0 0 0 reserved 0 0 1 2 0 0 1 reserved ba1 ba0 mrs mode 0 1 0 3 0 1 0 reserved 0 0 mr 0 1 1 4 0 1 1 3 0 1 emr(1) 1 0 0 5 1 0 0 4 1 0 emr(2) 1 0 1 6 1 0 1 5 1 1 emr(3) 1 1 0 7 1 1 0 6 1 1 1 8 1 1 1 7
as4c32m16d 2 alliance memory in c . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 11 rev. 1. 1 feb . /201 3 table 6 . extended mode re gister emr (1) bitmap ba1 ba0 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 address field 0 1 qoff 0 dqs# ocd program rtt additive latency rtt d.i.c dll extended mode register ba1 b a0 mrs mode a6 a2 rtt (nominal) 0 0 mr 0 0 odt disable a0 dll enable 0 1 emr(1) 0 1 75 C
as4c32m16d 2 alliance memory in c . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 12 rev. 1. 1 feb . /201 3 - em r(2) the extended mode register (2) controls refresh related features. the default value of the extended mode register (2) is not defined, therefore the extended mode register (2) must be written after power - up for proper operation. the extended mode regis ter(2) is written by asserting low on cs#, ras#, cas#, we#, high on ba1 and low on ba0, while controlling the states of address pins a0 ~ a12. the ddr2 sdram should be in all bank precharge with cke already high prior to writing into the extended mode regi ster (2). the mode register set command cycle time (t mrd ) must be satisfied to complete the write operation to the extended mode register (2). mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in the precharge state. table 7 . extended mode register emr (2) bitmap ba1 ba0 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 address field 1 0 0 *1 srf 0 *1 dcc *4 pasr *3 extended mode register(2) a7 high temperature self - refresh rate enable 0 disable 1 enable *2 ba1 ba0 mrs mode a3 dcc enable *4 0 0 mr 0 disable 0 1 emr(1) 1 enable 1 0 emr(2) 1 1 emr(3) a2 a1 a0 partial array self refresh for 4 banks 0 0 0 full array 0 0 1 half array (ba[1:0]=00&01) 0 1 0 quarter array (ba[1:0]=00) 0 1 1 not defined 1 0 0 3/4 array (ba[1:0]=01,10&11) 1 0 1 half array (ba[1:0]=10&11 ) 1 1 0 quarter array (ba[1:0]=11) 1 1 1 not defined note 1: the rest bits in emrs(2) are reserved for future use and all bits in emrs(2) except a0 - a2, a7, ba0 and ba1 must be programmed to 0 when setting the extended mode register(2) during initialization. note 2: due to the migration nature, user needs to ensure the dram part supports higher than 85 ( tcase temperature self - refresh entry. if the high temperature self - refresh mode is supported then controller can set the emrs2[a7] bit to enabl e the self - refresh rate in case of higher than 85 ( temperature self - refresh operation. note 3: if pasr (partial array self refresh) is enabled, data located in areas of the array beyond the specified location will be los t if self refresh is entered. data integrity will be maintained if t ref conditions are met and no self refresh command is issued. note 4: dcc (duty cycle corrector) implemented, user may be given the controllability of dcc thru emr (2) [a3] bit.
as4c32m16d 2 alliance memory in c . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 13 rev. 1. 1 feb . /201 3 - emr(3) no function is defined in extended m ode register(3).the default value of the extended mode register(3) is not defined, therefore the extended mode register(3) must be programmed during initialization for proper operation. table 8. extended mode register emr (3) bitmap ba1 ba0 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 address field 1 1 0 *1 extended mode register(3) note 1: all bits in emr (3) except ba0 and ba1 are reserved for future use and must be set to 0 when programming the emr (3).
as4c32m16d 2 alliance memory in c . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 14 rev. 1. 1 feb . /201 3 of f - chip drive (ocd) impedance adjustment ddr2 sdram supports driver calibration feature and the following flow chart is an example of sequence. every calibration mode command should be followed by ocd calibration mode exit before any other command being s t a r t e m r s : o c d c a l i b r a t i o n m o d e e x i t e m r s : d r i v e ( 1 ) d q & d q s h i g h ; d q s # l o w t e s t e m r s : o c d c a l i b r a t i o n m o d e e x i t e m r s : e n t e r a d j u s t m o d e b l = 4 c o d e i n p u t t o a l l d q s i n c , d e c , o r n o p e m r s : o c d c a l i b r a t i o n m o d e e x i t e m r s : d r i v e ( 0 ) d q & d q s l o w ; d q s # h i g h t e s t e m r s : o c d c a l i b r a t i o n m o d e e x i t e m r s : e n t e r a d j u s t m o d e b l = 4 c o d e i n p u t t o a l l d q s i n c , d e c , o r n o p e m r s : o c d c a l i b r a t i o n m o d e e x i t e n d e m r s : o c d c a l i b r a t i o n m o d e e x i t a l l o k b e f o r e e n t e r i n g o c d i m p e d a n c e a d j u s t m e n t , a l l m r s h o u l d b e p r o g r a m m e d a n d o d t s h o u l d b e c a r e f u l l y c o n t r o l l e d d e p e n d i n g o n s y s t e m e n v i r o n m e n t a l l o k
as4c32m16d 2 alliance memory in c . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 15 rev. 1. 1 feb . /201 3 - extended mo de register for ocd impedance adjustment ocd impedance adjustment can be done using the following emrs mode. in drive mode all outputs are driven out by ddr2 sdram. in drive ( 1) mode, all dq, dqs signals are driven high and all dqs # signals are driven low . in drive ( 0) mode, all dq, dqs signals are driven low and all dqs # signals are drive high . in adjust mode, bl = 4 of operation code data must be used. in case of ocd calibration default, output driver characteristics have a nominal impedance value of 18 o hms during nominal temperature and voltage conditions. output driver characteristics for ocd calibration default are specified in the following table. ocd applies only to normal full strength output drive setting defined by emrs and if half strength is set , ocd default driver characteristics are not applicable. when ocd calibration adjust mode is used, ocd default output driver characteristics are not applicable. after ocd calibration is completed or driver strength is set to default, subsequent emrs comman ds not intended to adjust ocd characteristics must specify a7~a9 as 000 in order to maintain the default or calibrated value. - ocd impedance adjust to adjust output driver impedance, controllers must issue the adjust emrs command along with a 4bit burst code to ddr2 sdram as in the follo wing table. for this operation, burst length has to be set to bl = 4 via mrs command before activating ocd and controllers must drive this burst code to all dqs at the same time. d t0 in the following table means all dq bits at bit time 0, d t1 at bit time 1 , and so forth. the driver output impedance is adjusted for all ddr2 sdram dqs simultaneously and after ocd calibration, all dqs of a given ddr2 sdram will be adjusted to the same driver strength setting. the maximum step count for adjustment is 16 and whe n the limit is reached, further increment or decrement code has no effect. the default setting maybe any step within the 16 step range. when adjust mode command is issued, al from previously set value must be applied. table 10.ocd adjust mode program 4bi t burst code inputs to all dqs operation d t0 d t1 d t2 d t3 pull - up driver strength pull - down driver strength 0 0 0 0 nop nop 0 0 0 1 increase by 1 step nop 0 0 1 0 decrease by 1 step nop 0 1 0 0 nop increase by 1 step 1 0 0 0 nop decrease by 1 step 0 1 0 1 increase by 1 step increase by 1 step 0 1 1 0 decrease by 1 step increase by 1 step 1 0 0 1 increase by 1 step decrease by 1 step 1 0 1 0 decrease by 1 step decrease by 1 step other combinations reserved
as4c32m16d 2 alliance memory in c . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 16 rev. 1. 1 feb . /201 3 ? odt (on die termination) on die termi nation (odt) is a feature that allows a dram to turn on/off termination resistance for each dq, udqs/udqs#, ldqs/ldqs#, udm, and ldm signal via the odt control pin. the odt feature is designed to improve signal integrity of the memory channel by allowing t he dram controller to independently turn on/off termination resistance for any or all dram devices. the odt function is support ed for active and standby modes. it is turned off and not supported in self refresh mode. figure 5 . functional representation of odt table 11.odt dc electrical characteristics parameter/condition symbol min. nom. max. unit note rtt effective impedance value for emrs(a6,a2)=0,1; 75 0;150 rtt effective impedance value for emrs(a6,a2)=1,1;50 s w 1 r v a l 1 v d d q s w 1 r v a l 1 v s s q s w 3 r v a l 3 v d d q s w 3 r v a l 3 v s s q s w 2 r v a l 2 v d d q s w 2 r v a l 2 v s s q i n p u t p i n d r a m i n p u t b u f f e r s w i t c h ( s w 1 , s w 2 , s w 3 ) i s e n a b l e d b y o d t p i n . s e l e c t i o n a m o n g s w 1 , s w 2 , a n d s w 3 i s d e t e r m i n e d b y r t t ( n o m i n a l ) i n e m r . t e r m i n a t i o n i n c l u d e d o n a l l d q s , d m , d q s , a n d d q s # p i n s ( ) ( ) ih il ih il v ac v ac rtt(eff)= i(v (ac))-i(v (ac)) 1 100% u ? ?1 ddq 2xvm rtt(mis)= v
as4c32m16d 2 alliance memory in c . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 17 rev. 1. 1 feb . /201 3 bank activate command t he bank activate command is issued by holding cas# and we# high with cs# and ras# low at the rising edge of the clock. the bank addresses ba0 and ba1 are used to select the desired bank. the row addresses a0 through a12 are used to determine which row to a ctivate in the selected bank. the bank activate command must be applied before any read or write operation can be executed. immediately after the bank active command, the ddr2 sdram can accept a read or write command (with or without auto - precharge) on the following clock cycle. if a r/w command is issued to a bank that has not satisfied the t rcd min specification, then additive latency must be programmed into the device to delay the r/w command which is internally issued to the device. the additive latency value must be chosen to assure t rcd min is satisfied. additive latencies of 0, 1, 2, 3, 4, and 5 are supported. once a bank has been activated it must be precharged before another bank activate command can be applied to the same bank. the bank active and pr echarge times are defined as t ras and t rp , respectively. the minimum time interval between successive bank activate commands to the same bank is determined (t rc ). the minimum time interval between bank active commands is t rrd ? read and write access modes after a bank has been activated, a read or write cycle can be executed. this is accomplished by setting ras# high, cs# and cas# low at the clocks rising edge. we# must also be defined at this time to determine whether the access cycle is ? post ed cas# posted cas# operation is supported to make command and data bus efficient for sustainable bandwidths in ddr2 sdram. in this operation, the ddr2 sdr am allows a cas# read or write command to be issued immediately after the ras bank activate command (or any time during the ras# - cas# - delay time, t rcd , period). the command is held for the time of the additive latency (al) before it is issued inside the d evice. the read latency (rl) is controlled by the sum of al and the cas latency (cl). therefore if a user chooses to issue a r/w command before the t rcd min, then al (greater than 0) must be written into the emr(1). the write latency (wl) is always defined as rl - 1 (read latency - 1) where read latency is defined as the sum of additive latency plus cas latency (rl=al+cl). read or write operations using al allow seamless bursts (refer to seamless operation timing diagram examples in read burst and write burst section) ? burst mode operation burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or from memory locations (read cycle). the parameters that define how the burst mode will operate are burst sequence and burs t length. the ddr2 sdram supports 4 bit and 8 bit burst modes only. for 8 bit burst mode, full interleave address ordering is supported, however, sequential address ordering is nibble based for ease of implementation. the burst length is programmable and d efined by the addresses a0 ~ a2 of the mrs. the burst type, either sequential or interleaved, is programmable and defined by the address bit 3 (a3) of the mrs. seamless burst read or write operations are supported. interruption of a burst read or write ope ration is prohibited, when burst length = 4 is programmed. for burst interruption of a read or write burst when burst length = 8 is used, see the burst interruption section of this
as4c32m16d 2 alliance memory in c . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 18 rev. 1. 1 feb . /201 3 table 12.burst definition, addressing sequence of sequential and interleave mode burst length start address sequential interleave a2 a1 a0 4 x 0 0 0, 1, 2, 3 0, 1, 2, 3 x 0 1 1, 2, 3, 0 1, 0, 3, 2 x 1 0 2, 3, 0, 1 2, 3, 0, 1 x 1 1 3, 0, 1, 2 3, 2, 1, 0 8 0 0 0 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 0 0 1 1, 2, 3, 0, 5, 6, 7, 4 1, 0, 3, 2, 5, 4, 7, 6 0 1 0 2, 3, 0, 1, 6, 7, 4, 5 2, 3, 0, 1, 6, 7, 4, 5 0 1 1 3, 0, 1, 2, 7, 4, 5, 6 3, 2, 1, 0, 7, 6, 5, 4 1 0 0 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 1 0 1 5, 6, 7, 4, 1, 2, 3, 0 5, 4, 7, 6, 1, 0, 3, 2 1 1 0 6, 7, 4, 5, 2, 3, 0, 1 6, 7, 4, 5, 2, 3, 0, 1 1 1 1 7, 4, 5, 6, 3, 0, 1, 2 7, 6, 5, 4, 3, 2, 1, 0 ? burst read command the burst read command is initiated by havin g cs # and cas # low while holding ras # and we # high at the rising edge of the clock. the address inputs determine the starting column address for the burst. the delay from the start of the command to when the data from the first cell appears on the outputs is equ al to the value of the read l atency (rl). the data s trobe output (dqs) is driven low 1 clock cycle before valid data (dq) is driven onto the data bus. the first bit of the burst is synchronized with the rising edge of the data strobe (dqs). each subs equent data - out appears on the dq pin in phase with the dqs signal in a source synchronous manner. the rl is equal to an additive latency (al) plus cas l atency (cl). the cl is defined by the mode register set (mrs), similar to the existing sdr and ddr sdra ms. the al is defined by the extended mode register set (1 ) (emrs ( 1)). ddr2 sdram pin timings are specified for eithe r single ended mode or differen tial mode depending on the setting of the emrs enable dqs mode bit; timing advantages of differential mod to 10 kresis ? burst write operation the burst write command is initiated by having cs # , cas # and we # low while holding ras # high at the rising edge of the clock. the address inputs determine the starting column address. writ e latency (wl) is defined by a r ead latency (rl) minus one and is equal to (al + cl - 1);and is the number of clocks of delay that are required from the time the write command is register ed to the clock edge associated to the first dqs strobe. a data strobe signal (dqs) should be driven low (preamble) one clock prior to the wl. the first data bit of the burst cycle must be applied to the dq pins at the first rising edge of the dqs followin g the preamble. the t dqss specification must be satisfied for each positive dqs transition to its associated clock edge during write cycles. the subsequent burst bit data are issued on successive edges of the dqs until the burst length is completed, wh ich is 4 or 8 bit burst. when t he burst has finished, any additional data supplied to the dq pins will be ignored. the dq signal is ignored after the burst write operation is complete. the time fr om the completion of the burst write to bank precharge is the w r ite recovery time (wr). ddr2 sdram pin timings are specified for either single ended mode or differential mode depending on the setting of the emrs enable dqs mode bit; timing advantages of differential
as4c32m16d 2 alliance memory in c . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 19 rev. 1. 1 feb . /201 3 in single ended mode, timing relationships are measured relative to the rising or falling edges of dqs crossing at the specified ac/dc levels. in differential mode, these timing relationships are measured relative to the crosspoint of dqs and its complement, dqs # . this distinction in timing methods is guaranteed by design and characterization. note that when differential data strobe mode is disabled via the emrs, the complementary pin, dqs # , mu st be tied externally to v ss through a 20
as4c32m16d 2 alliance memory in c . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 20 rev. 1. 1 feb . /201 3 ? write data mask one w rite data mask (dm) pin for each 8 data bits (dq) will be supported on ddr2 sdrams, consistent with the implementation on ddr sdrams. it has identical timings on w rite operations as the data bits, and though used in a uni - directional manner, is internally loaded identically to data bits to insure mat ched system timing. dm is not used during read cycles. ? precharge operation the precharge c ommand is used to precharge or close a bank that has been activated. the precharge command is triggered when cs#, ras# and we# are low and cas# is high at the rising edge of the clock. the precharge command can be used to precharge each bank independently or all banks simultaneously. three address b its a10, ba1, and ba0 are used to define which bank to precharge when the command is issued. table 13.bank selection for precharge by address bits a10 ba1 ba0 precharged bank(s) low low low bank 0 only low low high bank 1 only low high low bank 2 only low high high bank 3 only high dont care dont care ? burst read operation followed by precharge minimum read to precharge command spacing to the same bank = al + bl/2 + max (rtp, 2) - 2 clocks. for the earliest possible precharge, the prechar ge command may be issued on the rising edge which additive latency (al) + bl/2 clocks after a read command. a new bank active (command) may be issued to the same bank after the ras# ? burst write operation followed by precharge minimum write to precharge command spacing t o the same bank = wl + bl/2 + t wr . for write cycles, a delay must be satisfied from the completion of the last burst write cycle until the precharge command can be issued. this delay is known as a write recovery time (t wr ) referenced from the completion of the burst write to the precharge command. no precharge command should be issued prior to the t wr delay, as ddr2 sdram does not support any burst interrupt by a precharge command. t wr is an analog timing parameter and is not the programmed value for t wr in the mrs.
as4c32m16d 2 alliance memory in c . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 21 rev. 1. 1 feb . /201 3 ? auto precharge operation before a new row in an active bank can be opened, the active bank must be precharged using either the precharge command or the auto - precharge function. when a read or a write command is given to the ddr2 sdram, the cas# timing accepts one extra address, column address a10, to allow the active bank to automatically begin precharge at the earliest possible moment during the burst read or write cycle. if a10 is low when the read or write command is issued, then normal read or write burst operation is executed and the bank remains active at the completion of the burst sequence. if a10 is high when the read or write command is issued, then the auto - precharge function is engaged. during auto - precharge, a read command will execu te as normal with the exception that the active bank will begin to precharge on the rising edge which is cas latency (cl) clock cycles before the end of the read burst. auto - precharge also be implemented during write commands. the precharge operation engag ed by the auto precharge command will not begin until the last data of the burst write sequence is properly stored in the memory array. this feature allows the precharge operation to be partially or completely hidden during burst read cycles (dependent upo n cas latency) thus improving system performance for random data access. the ras# lockout circuit internally delays the precharge operation until the array restore operation has been completed (t ras satisfied) so that the auto precharge command may be issu ed with any read or write command.
as4c32m16d 2 alliance memory in c . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 22 rev. 1. 1 feb . /201 3 ? burst read with auto precharge if a10 is high when a read command is issued, the read with auto - precharge function is engaged. the ddr2 sdram starts an auto - precharge operation on the rising edge which is (al + bl/2) c ycles later from the read with ap command if t ras (min) and t rtp are satisfied. if t ras (min) is not satisfied at the edge, the start point of auto - precharge operation will be delayed until t ras (min) is satisfied. if t rtp (min) is not satisfied at the edge, t he start point of auto - precharge operation will be delayed until t rtp (min) is satisfied. in case the internal precharge is pushed out by t rtp , t rp starts at the point where the internal precharge happens (not at the next rising clock edge after this event) . so for bl = 4 the minimum time from read with auto - precharge to the next activate command becomes al + t rtp + t rp . for bl = 8 the time from read with auto - precharge to the next activate command is al + 2 + t rtp + t rp . note that both parameters t rtp and t rp have to be rounded up to the next integer value. in any event internal precharge does not start earlier than two clocks after the last 4 - bit prefetch. a new bank active (command) may be issued to the same bank if the following two conditions are satisf ied simultaneously: (1) the ras# precharge time (t rp ) has been satisfied from the clock at which the auto - precharge begins. (2) the ras# cycle time (t rc ) from the previous bank activation has been satisfied. ? burst write with auto precharge if a10 is high when a write command is issued, the write with auto - precharge function is engaged. the ddr2 sdram automatically begins precharge operation after the completion of the burst write plus write recovery time (t wr ). the bank undergoing auto - precharge from the c ompletion of the write burst may be reactivated if the following two conditions are satisfied. (1) the data - in to bank activate delay time (wr + t rp ) has been satisfied. (2) the ras# cycle time (t rc ) from the previous bank activation has been satisfied. t able 14.precharge & auto precharge clarification from command to command minimum delay between from command to to command
as4c32m16d 2 alliance memory in c . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 23 rev. 1. 1 feb . /201 3 ? refresh command when cs#, ras# and cas# are held low and we# high at the rising edge of the clock, the chip enters the refresh mode (ref). all banks of the ddr2 sdram must be precharged and idle for a minimum of the precharge time (t rp ) before the refresh command (ref) can be applied. an address counter, internal to the device, supplies the bank address during the refresh cycle. no control of the external address bus is required once this cycle has sta rted. when the refresh cycle has completed, all banks of the ddr2 sdram will be in the precharged (idle) state. a delay between the refresh command (ref) and the next activate command or subsequent refresh command must be greater than or equal to the refre sh cycle time ( t rfc ) .to allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. a maximum of eight refresh commands can be posted to any given ddr2 sdram, meaning that the maxi mum absolute interval between any refresh command and the next refresh command is 9 * t refi . ? self refresh operation the self refresh command can be used to retain data in the ddr2 sdram, even if the rest of the system is powered down. when in the self ref resh mode, the ddr2 sdram retains data without external clocking. the ddr2 sdram device has a built - in timer to accommodate self refresh operation. the self refresh command is defined by having cs#, ras#, cas# and cke# held low with we# high at the rising edge of the clock. odt must be turned off before issuing self refresh command, by either driving odt pin low or using emrs command. once the command is registered, cke must be held low to keep the device in self refresh mode. the dll is automatically disab led upon entering self refresh and is automatically enabled upon exiting self refresh. when the ddr2 sdram has entered self refresh mode all of the external signals except cke, are dont care. for proper self refresh operation all power
as4c32m16d 2 alliance memory in c . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 24 rev. 1. 1 feb . /201 3 power - down power - down is synchronously entered when cke is registered low along with nop or deselect command. no read or write operation may be in progress whe n cke goes low. these operations are any of the following: read burst or write burst and recovery. cke is allowed to go low while any of other operations such as row activation, precharge or autoprecharge, mode register or extended mode register command ti me, or auto refresh is in progress. the dll should be in a locked state when power - down is entered. otherwise dll should be reset after exiting power - down mode for proper read operation. if power - down occurs when all banks are precharged, this mode is refe rred to as precharge power - down; if power - down occurs when there is a row active in any bank, this mode is referred to as active power - down. for active power - down two different power saving modes can be selected within the mrs register, address bit a12. wh en a12 is set to low this mode is referred as standard active power down mode and a fast power timing parameter can be used. when a12 is set to high this mode is referred as a power saving low power active power down mode. this mode takes longer to exit from the power signal must be maintained at the inputs of the ddr2 sdram, and all other input signals are d ont care. power ? asynchronous cke low event dram requires cke to be maintained high for all valid operations as defined in this datasheet. if c asynchronously drops low during any valid t the input of dram before cke is raised high again. dram must be fully re ? input clock frequency change during precharge power down ddr2 sdram input clock frequency can b e changed under following condition: ddr2 sdram is in precharged power down mode. odt must be turned off and cke must be at logic low level. a minimum of 2 clocks must be waited after cke goes low before clock frequency may change. sdram input clock freque ncy is allowed to change only within minimum and maximum operating frequency specified for the particular speed grade. during input clock frequency change, odt and cke must be held at stable low levels. once input clock frequency is changed, stable new clo cks must be provided to dram before precharge power down may be exited and dll must be reset via emrs after precharge power down exit. depending on new clock frequency an additional mrs command may need to be issued to appropriately set the wr, cl etc. dur ing dll re - lock period, odt must remain off. after the dll lock time, the dram is ready to operate with new clock frequency. ? no operation command the no operation command should be used in cases when the ddr2 sdram is in an idle or a wait state. the purpo se of the no operation command (nop) is to prevent the ddr2 sdram from registering any unwanted commands between operations. a no operation command is registered when cs# is low with ras#, cas#, and we# held high at the rising edge of the clock. a no opera tion command will not terminate a previous operation that is still executing, such as a burst read or write cycle. ? deselect command the deselect command performs the same function as a no operation command. deselect command occurs when cs# is brought high at the rising edge of the clock, the ras#, cas#, and we# signals become dont cares.
as4c32m16d 2 alliance memory in c . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 25 rev. 1. 1 feb . /201 3 table 15. absolute maximum dc ratings symbol parameter rating unit note v dd voltage on vdd pin relative to vss - 1.0 ~ 2.3 v 1,3 v ddq voltage on vddq pin relative to vs s - 0.5 ~ 2.3 v 1,3 v dd l voltage on vddl pin relative to vss - 0.5 ~ 2.3 v 1,3 v in , v out voltage on any pin relative to vss - 0.5 ~ 2.3 v 1 , 4 t stg storage temperature - 55~1 0 0 c 1 ,2 note1: stress greater than those listed under absolute maximum ratings may cause permanent damage to the c 1,2 industrial - 4 0~95 c 1,2 note1: operating temperature is the case surface temperature on center/top of the dram. note2: the operating temperatu r e range is the temperature where all dram specification will be supported. outside of this temperature range, even if it is still within the limit of stress condition, some deviation on portion of operating specification may be required. during operation, the dram case temperature must be maintained between 0 - 85 c under all other speci fication parameter. supporting 0 - 85 c with full jedec ac & dc specifications and being able to extend to 95 c with doubling auto - refresh commands in frequency to a 32 ms period ( trefi = 3.9 us). s upport ing higher temperature self - refresh entry via the control of emsr(2) bit a7. table 17. recommended dc operating conditions (sstl_1.8) symbol parameter min. typ. max. unit note v dd power supply voltage 1.7 1.8 1.9 v 1 v dd l power supply voltage for dll 1.7 1.8 1.9 v 5 v ddq power supply voltage for i/o buffer 1.7 1.8 1.9 v 1,5 v ref input reference voltage 0.49 x v ddq 0.5 x v ddq 0.51 x v ddq mv 2,3 v tt termination voltage v ref - 0.04 v ref v ref + 0.04 v 4 note1: there is no specific device vdd supply voltage requirement for sstl_18 compliance. howeve r under all conditions v ddq must be less than or equal to v dd. note2: the value of v ref may be selected by the user to provide optimum noise margin in the system. typically the value of v ref is expected to be about 0.5 x v ddq of the transmitting device and v ref is expected to track variations in v ddq . note3: peak to peak ac noise on v ref may not exceed +/ - 2 % v ref (dc). note4: v tt of transmitting device must track v ref of receiving device. note5: v ddq tracks with v dd , v ddl tracks with v dd . ac parameters are measured with v dd , v ddq and v ddl tied together
as4c32m16d 2 alliance memory in c . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 26 rev. 1. 1 feb . /201 3 table 18 . input logic level ( v dd = 1.8v r 0.1 v , t op e r = - 4 0~ 9 5 q c) symbol parameter - 25 unit min. max. vih ( d c) dc input logic high voltage v ref + 0.125 v ddq + 0.3 v vil ( d c) dc input low voltage - 0. 3 v ref - 0.125 v vih (ac) ac input high voltage v ref + 0.2 v ddq + v peak v vil (ac) ac input low voltage v ssq - v peak v ref - 0.2 v vid (ac) ac differential voltage 0.5 v ddq v vix (ac) ac differential crosspoint voltage 0.5 x v ddq - 0.175 0.5 x v ddq + 0.175 v note1: refer to ove rshoot/undershoot specification for v peak value: maximum peak amplitude allowed for overshoot and undershoot . table 19 . ac input test conditions ( v dd = 1.8v r 0.1 v , t op e r = - 40~95 q c) symbol parameter - 25 unit note v ref inpu t reference voltage 0.5 x v ddq v 1 v swing(max) input signal maximum peak to peak swing 1.0 v 1 slew rate input signal minimum slew rate 1.0 v/ns 2, 3 note1: input waveform timing is referenced to the input signal crossing through the v ih / il (ac) level applied to the device under test. note2: the input signal minimum slew rate is to be maintained over the range from v ref to v ih (ac) min for rising edges and the range from v ref to v il (ac) max for falling edges . note3: ac timings are referenced with inpu t waveforms switching from v il (ac) to v ih (ac) on the positive transitions and v ih (ac) to v il (ac) on the negative transitions. table 20. differential ac output parameters ( v dd = 1.8v r 0.1 v , t op e r = - 40~95 q c) symbol parameter - 25 unit note min. max . v ox (ac) ac differential cross point voltage 0.5 x v ddq - 0.125 0.5 x v ddq + 0.125 v 1 note1: the typical value of v ox (ac ) is expected to be about 0.5 x v ddq of the transmitting device and v ox (ac) is expected to track variations in v ddq . v ox (ac) in dicates the voltage at which differential output signals must cross. table 21. ac overshoot/undershoot specification for address and control pins (a0 - a12, ba0 - ba1, cs#, ras#, cas#, we#, cke, odt) parameter - 25 unit maximum peak amplitude allowed for over shoot area 0.5 v maximum peak amplitude allowed for undershoot area 0.5 v maximum overshoot area above v dd 0.66 v - ns maximum undershoot area below v ss 0.66 v - ns
as4c32m16d 2 alliance memory in c . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 27 rev. 1. 1 feb . /201 3 table 22 . ac overshoot/undershoot specification for clock, data, strobe, and mask pins (dq, udqs, ldqs, udqs#, ldqs#, dm, ck, ck#) parameter - 25 unit maximum peak amplitude allowed for overshoot area 0.5 v maximum peak amplitude allowed for undershoot area 0.5 v maximum overshoot area above v dd 0.23 v - ns maximum undershoot area below v ss 0.23 v - ns table 23 . output ac test conditions ( v dd = 1.8v r 0.1 v , t op e r = - 40~95 q c) symbol parameter - 25 unit note v otr output timing measurement reference level 0.5xv ddq v 1 note1: the v ddq of the device under test is referenced. table 24. output dc current drive ( v dd = 1.8v r 0.1 v , t op e r = - 40~95 q c) symbol parameter - 25 unit note i oh (dc) output minimum source dc current - 13.4 ma 1, 3, 4 i ol (dc) output minimum sink dc current 13.4 ma 2, 3, 4 note1: v ddq = 1.7 v; v out = 1420 mv. (v out - v ddq ) / i oh must be less than 21
as4c32m16d 2 alliance memory in c . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 28 rev. 1. 1 feb . /201 3 table 26 . idd specification parameters and test conditions ( v dd = 1.8v r 0.1 v , t op e r = - 40~95 q c) parameter & test condition symbol - 25 unit max. operating one bank active - precharge current: t ck = t ck (min), t rc = t rc (min), t ras = t ras (min); cke is high, cs# is high between valid commands; address bus inputs are switching; data bus inputs are switching i dd0 75 ma operating one bank active - read - precharge current: i out = 0ma; bl = 4, cl = cl (m in) , al = 0; t ck = t ck (min) ,t rc = t rc (min) , t ras = t ras (min) , t rcd = t rcd (min) ;cke is high, cs# is high between valid commands; address bus inputs are switching; data pattern is same as i dd4w i dd1 85 ma precharge power - down current: all banks idle; tck =t ck (min) ; cke is low; other control and address bus inputs are stable; data bus inputs are floating i dd2p 8 ma precharge quiet standby current: all banks idle; t ck =t ck (min) ; cke is high, cs# is high; other control and address bus inputs are stable; d ata bus inputs are floating i dd2q 35 ma precharge standby current: all banks idle; t ck = t ck (min) ; cke is high, cs# is high; other control and address bus inputs are switching; data bus inputs are switching i dd2n 40 ma active power - down current: all b anks open; t ck =t ck (min) ; cke is low; other control and address bus inputs are stable; data bus inputs are floating mrs(a12)=0 i dd3p 20 ma mrs(a12)=1 14 ma active standby current: all banks open; t ck = t ck (min) , t ras = t ras (max) , t rp = t rp (min) ; ck e is high, cs# is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching i dd3n 55 ma operating burst write current: all banks open, continuous burst writes; bl = 4, cl = cl (min) , al = 0; t ck = t ck (m in) , t ras = t ras (max) , t rp = t rp (min) ; cke is high, cs# is high between valid commands; address bus inputs are switching; data bus inputs are switching i dd4w 120 ma operating burst read current: all banks open, continuous burst reads, i out = 0ma; bl = 4, cl = cl (min) , al = 0; t ck = t ck (min) , t ras = t ras (max) , t rp = t rp (min) ; cke is high, cs# is high between valid commands; address bus inputs are switching; data bus inputs are switching i dd4r 130 ma burst refresh current: t ck = t ck (min) ; refresh c ommand at every t rfc (min) interval; cke is high, cs# is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching i dd5 95 ma self refresh current: ck and ck# at 0v; cke
as4c32m16d 2 alliance memory in c . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 29 rev. 1. 1 feb . /201 3 table 27. electrical characteristics and recommended a.c. operating conditions (v dd = 1 . 8 v r 0.1 v , t op er = - 40~95 q c) symbol parameter - 25 unit specific notes min. max. t ck(avg) average clock period cl=3 5 8 ns 15, 33, 34 cl=4 3.75 8 ns 15, 33, 34 cl=5 2.5 8 ns 15, 33, 34 cl=6 2.5 8 ns 15, 33, 34 cl=7 - - ns 15, 33, 34 t ch(avg) ave rage clock high pulse width 0.48 0.52 t ck 34, 35 t cl(avg) average clock low pulse width 0.48 0.52 t ck 34, 35 wl write command to dqs associated clock edge rl - 1 t ck t dqss dqs latching rising transitions to associated clock edges - 0.25 0.25 t ck 28 t dss dqs falling edge to ck setup time 0.2 - t ck 28 t dsh dqs falling edge hold time from ck 0.2 - t ck t dqsh dqs input high pulse width 0.35 - t ck t dqsl dqs input low pulse width 0.35 - t ck t wpre write preamble 0.35 - t ck t wpst write postamble 0.4 0.6 t ck 10 t is(base) address and control input setup time 0.175 - ns 5, 7, 9, 22, 27 t ih(base) address and control input hold time 0.25 - ns 5, 7, 9, 23, 27 t ipw control & address input pulse width for each input 0.6 - t ck t ds(base) dq & dm input setup tim e 0.05 - ns 6, 7, 8, 20, 26, 29 t dh(base) dq & dm input hold time 0.125 - ns 6, 7, 8, 21, 26, 29 t dipw dq and dm input pulse width for each input 0.35 - t ck t ac dq output access time from ck, ck# - 0.4 0.4 ns 38 t dqsck dqs output access time from ck, c k# - 0.35 0.35 ns 38 t hz data - out high - impedance time from ck, ck# - t ac(max) ns 18, 38 t lz(dqs) dqs(dqs#) low - impedance time from ck, ck# t ac(min) t ac(max) ns 18, 38 t lz(dq) dq low - impedance time from ck, ck# 2t ac(min) t ac(max) ns 18, 38 t dqsq dqs - dq s kew for dqs and associated dq signals - 0.2 ns 13 t hp ck half pulse width min(t cl ,t ch ) - ns 11, 12, 35 t qhs dq hold skew factor - 0.3 ns 12, 36 t qh dq/dqs output hold time from dqs t hp - t qhs - ns 37 t rpre read preamble 0.9 1.1 t ck 19, 39 t rpst read po stamble 0.4 0.6 t ck 19, 40 t rrd active to active command period 10 - ns 4, 30 t ccd cas# to cas# command delay 2 - t ck t wr write recovery time 15 - ns 30 t dal auto power write recovery + precharge time wr + t rp - ns 14, 31 t wtr internal write to re ad command delay 7.5 - ns 3, 24, 30
as4c32m16d 2 alliance memory in c . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 30 rev. 1. 1 feb . /201 3 t rtp internal read to precharge command delay 7.5 - ns 3, 30 t cke cke minimum pulse width 3 - t ck 25 t xsnr exit self refresh to non - read command delay t rfc +10 - ns 30 t xsrd exit self refresh to a read command 200 - t ck t xp exit precharge power down to any command 2 - t ck t xard exit active power down to read command 2 - t ck 1 t xards exit active power down to read command(slow exit, lower power) 8 - al - t ck 1, 2 t aond odt turn - on delay 2 2 t ck 16 t aon odt turn - on t ac(min) t ac (max)+0.7 ns 6, 16, 38 t aonpd odt turn - on (power - down mode) t ac (min)+2 2 t ck +t ac (max)+1 ns t aofd odt turn - off delay 2.5 2.5 t ck 17, 42 t aof odt turn - off t ac(min) t ac(max) +0.6 ns 17, 41, 42 t aofpd odt turn - off (power - down mode) t ac (min)+2 2.5 t ck +t ac (max)+1 ns t anpd odt to power down entry latency 3 - t ck t axpd odt power down exit latency 8 - t ck t mrd mode register set command cycle time 2 - t ck t mod mrs command to odt update delay 0 12 ns 30 t oit ocd drive mode output delay 0 12 ns 30 t delay minimum time clocks remains on after cke asynchronously drops low t is + t ck +t ih - ns 15 t rfc refresh to active/refresh command time 105 - ns 43 t refi average periodic refresh interval @ - 4 0 (# tc # +85 ( - 7.8 43 @ +85 ( p? tc # +95 ( - 3.9 43 t rcd ras# to cas# delay time 12.5 - ns t rp row precharge delay time 12.5 - ns t rc row cycle delay time 57.5 - ns t ras row active delay time 45 70k ns
as4c32m16d 2 alliance memory in c . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 31 rev. 1. 1 feb . /201 3 general notes, which may apply for all ac parameters: note 1: ddr2 sdra m ac timing reference load the below figure represents the timing reference load used in defining the relevant timing parameters of the part. it is not intended to be either a precise representation of the typical system environment or a depiction of the a ctual load presented by a production tester. figure 6. ac timing reference load the output timing reference voltage level for single ended signals is the crosspoint with vtt. the output timing reference voltage level for differential signals is the crosspoint of the true (e.g. dqs) and the complement (e.g. dqs#) signal. note 2: slew rate measurement levels a) output slew rate for falling and rising edges is measured between v tt - 250 mv and v tt + 250 mv for single ended s ignals. for differential signals (e.g. dqs C C C C C v d d q d u t d q s d q s # d q v t t = v d d q / 2 2 5 ? t i m i n g r e f e r e n c e p o i n t o u p u t
as4c32m16d 2 alliance memory in c . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 32 rev. 1. 1 feb . /201 3 figure 7. slew rate test load note 4: differential data strobe ddr2 sdram pin timings are specified for either single ended mode or differential mode depending on the setti ng of the emrs enable dqs mode bit; timing advantages of differential mode are realized in system design. the timings are specified with dqs, dm, and dqss (in single ended mode) input slew rate of 1.0v/ns. v d d q d u t d q s d q s # d q v t t = v d d q / 2 2 5 ? t e s t p o i n t o u p u t
as4c32m16d 2 alliance memory in c . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 33 rev. 1. 1 feb . /201 3 note 8: data setup and hold time derating. for all input signals the total t ds (setup time) and t dh (hold time) required is calculated by adding the data sheet. t ds(ba se) and t dh(base) value to the (all units in ps; the note applies to the entire tab
as4c32m16d 2 alliance memory in c . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 34 rev. 1. 1 feb . /201 3 note 11: min (t cl , t ch ) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for t cl and t ch ). note 12: t qh = t hp C C
as4c32m16d 2 alliance memory in c . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 35 rev. 1. 1 feb . /201 3 note 26: if t ds or t dh is violated, data corruption may occur and the data must be re - written with valid data before a valid read can be executed. note 27: these parameters are measured from a command/address signal (cke, cs#, ras#, cas#, we#, odt, ba0, a0, a1, etc.) transition edge to its respective clock signal (ck/ck#) crossing. the spec values are not affected by the amount of clock jitter appl ied (i.e. t jit (per), t jit (cc), etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. that is, these parameters should be met whether clock jitter is present or not. note 28: these parameters are measured from a dat a strobe signal (ldqs/udqs) crossing to its respective clock signal (ck/ck#) crossing. the spec values are not affected by the amount of clock jitter applied (i.e. t jit (per), t jit (cc), etc.), as these are relative to the clock signal crossing. that is, the se parameters should be met whether clock jitter is present or not. note 29: these parameters are measured from a data signal ((l/u) dm, (l/u) dq0, (l/u) dq1, etc.) transition edge to its respective data strobe signal (ldqs/udqs/ldqs#/udqs#) crossing. note 30: for these pa rameters, the ddr2 sdram device is characterized and verified to support tnparam = ru{tparam / t ck (avg)}, which is in clock cycles, assuming all input clock jitter specifications are satisfied. note 31: t dal [t ck ] = wr [t ck ] + trp [t ck ] = wr + ru {t rp [ps] / t ck (av g) [ps] }, where wr is the value programmed in the mode register set. note 32: new units, t (avg) is introduced in ddr2 . unit t (avg) represents the actual t
as4c32m16d 2 alliance memory in c . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 36 rev. 1. 1 feb . /201 3 definitions: - t ck (avg) t ck ( avg) is calculated as the average clock period across any consecutive 200 cycle window. where n=200 - t ch (avg) and t cl (avg) t ch (avg) is defined as the average high pulse width, as calculated across any consecutive 200 h igh pulses. where n=200 t cl (avg) is defined as the average low pulse width, as calculated across any consecutive 200 low pulses. where n=200 t jit (duty) is defined as the cumulative set of t ch jitter and t cl jitter. t ch jitter is the largest deviation of any single t ch from t ch (avg). t cl jitter is the largest deviation of any single t cl from t cl (avg). - t jit (duty) = min/max of {t jit (ch), t jit (cl)} where, t jit (ch) = {t chi - t ch (avg) where i=1 to 200} t jit (cl) = {t cli - t cl (avg) where i=1 to 200} - t jit (per), t jit (per,lck) t jit (per) is defined as the largest deviation of any single tck from t ck (avg). t jit (per) = min/max of {t cki - t ck (avg) where i=1 to 200} t jit (per) defines the single period jitter when the dll is already locked. t jit (per,lck) uses the same definition for single period jitter, during the dll locking period only. t jit (per) and tjit (per,lck) are not guaranteed through final production testing. - t jit (cc), t jit (cc,lck) t jit (cc) is defined as the difference in clock period between two consecutive clock cycles: t jit (cc) = max of |t cki +1 C ao ?? ?? | j ck ck 1 /n tt n j avg ao u ?? ?? | j ch ch ck 1 / t t t n j avg n avg ao u ?? ?? | j cl cl ck 1 / t t t n j avg n avg
as4c32m16d 2 alliance memory in c . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 37 rev. 1. 1 feb . /201 3 where note 34: these parameters are specified per their average values, however it is understood that the following relationship between the average timing and t he absolute instantaneous timing holds at all times. (min and max of spec values are to be used for calculations in the table below.) parameter symbol min. max. units absolute clock period t ck (abs) t ck (avg),min + t jit (per),min t ck (avg),max + t jit (per),ma x ps absolute clock high pulse width t ch (abs) t ch (avg),min * t ck (avg),min + t jit (duty),min t ch (avg),max * t ck (avg),max + t jit (duty),max ps absolute clock low pulse width t cl (abs) t cl (avg),min * t ck (avg),min + t jit (duty),min t cl (avg), max * t ck (avg),ma x + t jit (duty), max ps note 35: t hp is the minimum of the absolute half period of the actual input clock. t hp is an input parameter but not an input specification parameter. it is used in conjunction with t qhs to derive the dram output timing t qh . the value to be used for tqh calculation is determined by the following equation; t hp = min ( t ch (abs), t cl (abs) ), where, t ch (abs) is the minimum of the actual instantaneous clock high time; t cl (abs) is the minimum of the actual instantaneous clock low time; note 36: t qhs ac counts for: 1) the pulse duration distortion of on - chip clock circuits, which represents how well the actual t hp at the input is transferred to the output; and 2) the worst case push - out of dqs on one transition followed by the worst case pull - in of dq on the next transition, both of which are independent of each other, due to data pin skew, output pattern effects, and p - channel to n - channel variation of the output drivers note 37: t qh = t hp C ao u ?? ?? | j 1 err ck ck 1 nper t t t in j n avg - ? d d d d err err err err err err n=2 for 2 n=3 for 3 n=4 for 4 n=5 for 5 6 n 10 for 6 10 11 n 50 for 11 50 t t t t t t per per per per per per
as4c32m16d 2 alliance memory in c . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 38 rev. 1. 1 feb . /201 3 note 42: for t aofd of ddr2 - 800 , the 1/2 clock of t ck in the 2.5 x t ck assumes a t ch (avg), average input clock high pulse width of 0.5 relative to t ck (avg). t aof ,min and t aof ,max should each be derated by the same amount as the actual amount of t ch (avg) offs et present at the dram input with respect to 0.5. note 43: if refresh timing is violated, data corruption may occur and the data must be re - written with valid data before a valid read can be executed.
as4c32m16d 2 alliance memory in c . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 39 rev. 1. 1 feb . /201 3 timing waveforms figure 8. initialization se quence after power - up figure 9. ocd drive mode c k c k # t c h c k e c o m m a n d t c l t i s o d t t i s n o p p r e a l l e m r s m r s p r e a l l r e f r e f m r s e m r s e m r s a n y c m d 4 0 0 n s t r p t m r d t m r d t r p t m r d f o l l o w o c d f l o w c h a r t t o i t m i n 2 0 0 c y c l e d l l e n a b l e d l l r e s e t o c d d e f a u l t o c d c a l . m o d e e x i t n o t e 1 : t o g u a r a n t e e o d t o f f , v r e f m u s t b e v a l i d a n d a l o w l e v e l m u s t b e a p p l i e d t o t h e o d t p i n . t r f c t r f c c k # h i - z c k d q s d q s # d q s h i g h f o r d r i v e ( 1 ) c m d o c d c a l i b r a t i o n m o d e e x i t t o i t e n t e r d r i v e m o d e e m r s n o p n o p n o p e m r s d q d q s h i g h & d q s # l o w f o r d r i v e ( 1 ) , d q s l o w & d q s # h i g h f o r d r i v e ( 0 ) d q s l o w f o r d r i v e ( 0 ) t o i t h i - z n o t e : d r i v e m o d e , b o t h d r i v e ( 1 ) a n d d r i v e ( 0 ) , i s u s e d f o r c o n t r o l l e r s t o m e a s u r e d d r 2 s d r a m d r i v e r i m p e d a n c e . i n t h i s m o d e , a l l o u t p u t s a r e d r i v e n o u t t o i t a f t e r " e n t e r d r i v e m o d e " c o m m a n d a n d a l l o u t p u t d r i v e r s a r e t u r n e d - o f f t o i t a f t e r " o c d c a l i b r a t i o n m o d e e x i t " c o m m a n d .
as4c32m16d 2 alliance memory in c . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 40 rev. 1. 1 feb . /201 3 figure 10. ocd adjust mode figure 11. odt update delay timing - tmod c k # w l c k d q s _ i n d q _ i n d q s # t d s t d h c m d o c d c a l i b r a t i o n m o d e e x i t w r o c d a d j u s t m o d e e m r s n o p n o p n o p n o p n o p e m r s n o p d t 0 d t 1 d t 3 d t 2 v i h ( a c ) v i l ( a c ) v i h ( d c ) v i l ( d c ) d m n o t e 1 : f o r p r o p e r o p e r a t i o n o f a d j u s t m o d e , w l = r l - 1 = a l + c l - 1 t c k a n d t d s / t d h s h o u l d b e m e t a s s h o w n i n t h e f i g u r e . n o t e 2 : f o r i n p u t d a t a p a t t e r n f o r a d j u s t m e n t , d t 0 - d t 3 i s a f i x e d o r d e r a n d i s n o t a f f e c t e d b y b u r s t t y p e ( i . e . , s e q u e n t i a l o r i n t e r l e a v e ) c k u p d a t i n g r t t t i s e m r s n o p n o p n o p n o p n o p c m d t a o f d t m o d , m a x t m o d , m i n o l d s e t t i n g n e w s e t t i n g o d t n o t e 1 : t o p r e v e n t a n y i m p e d a n c e g l i t c h o n t h e c h a n n e l , t h e f o l l o w i n g c o n d i t i o n s m u s t b e m e t : - t a o f d m u s t b e m e t b e f o r e i s s u i n g t h e e m r s c o m m a n d . - o d t m u s t r e m a i n l o w f o r t h e e n t i r e d u r a t i o n o f t m o d w i n d o w , u n t i l t m o d , m a x i s m e t . t h e n t h e o d t i s r e a d y f o r n o r m a l o p e r a t i o n w i t h t h e n e w s e t t i n g , a n d t h e o d t s i g n a l m a y b e r a i s e d a g a i n t o t u r n e d o n t h e o d t . n o t e 2 : e m r s c o m m a n d d i r e c t e d t o e m r ( 1 ) , w h i c h u p d a t e s t h e i n f o r m a t i o n i n e m r ( 1 ) [ a 6 , a 2 ] , i . e . r t t ( n o m i n a l ) . n o t e 3 : " s e t t i n g " i n t h i s d i a g r a m i s t h e r e g i s t e r a n d i / o s e t t i n g , n o t w h a t i s m e a s u r e d f r o m o u t s i d e . c k #
as4c32m16d 2 alliance memory in c . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 41 rev. 1. 1 feb . /201 3 figure 12. odt update delay timing - t mod , as measured from outside figure 13. odt timing for active standby mode c k # c k r t t t i s e m r s c m d t a o f d t m o d , m a x o l d s e t t i n g n e w s e t t i n g o d t n o p n o p n o p n o p n o p t a o n d n o t e 1 : e m r s c o m m a n d d i r e c t e d t o e m r ( 1 ) , w h i c h u p d a t e s t h e i n f o r m a t i o n i n e m r ( 1 ) [ a 6 , a 2 ] , i . e . r t t ( n o m i n a l ) . n o t e 2 : " s e t t i n g " i n t h i s d i a g r a m i s m e a s u r e d f r o m o u t s i d e . c k # t 0 i n t e r n a l t e r m r e s . t i s t i s t a o n d c k t 1 t 2 t 3 t 4 t 5 t 6 c k e o d t v i h ( a c ) t i s v i l ( a c ) t a o f d t a o n , m i n t a o n , m a x t a o f , m i n t a o f , m a x r t t
as4c32m16d 2 alliance memory in c . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 42 rev. 1. 1 feb . /201 3 figure 14. odt timing for power - down mode c k # t 0 i n t e r n a l t e r m r e s . t i s c k t 1 t 2 t 3 t 4 t 5 t 6 c k e o d t v i h ( a c ) t i s v i l ( a c ) t a o f p d , m a x t a o n p d , m i n r t t t a o f p d , m i n t a o n p d , m a x
as4c32m16d 2 alliance memory in c . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 43 rev. 1. 1 feb . /201 3 figure 15. odt timing mode switch at entering power - down mode c k # c k t i s c k e t a o f d t a o n d o d t t a n p d t - 5 t - 4 t - 3 t - 2 t - 1 t 0 t 1 t 2 t 3 t 4 e n t e r i n g s l o w e x i t a c t i v e p o w e r d o w n m o d e o r p r e c h a r g e p o w e r d o w n m o d e . r t t i n t e r n a l t e r m r e s . t i s v i l ( a c ) o d t r t t i n t e r n a l t e r m r e s . t i s v i l ( a c ) t a o f p d m a x a c t i v e & s t a n d b y m o d e t i m i n g s t o b e a p p l i e d . p o w e r d o w n m o d e t i m i n g s t o b e a p p l i e d . t i s v i h ( a c ) r t t a c t i v e & s t a n d b y m o d e t i m i n g s t o b e a p p l i e d . t a o n p d m a x t i s v i h ( a c ) p o w e r d o w n m o d e t i m i n g s t o b e a p p l i e d . r t t o d t o d t i n t e r n a l t e r m r e s . i n t e r n a l t e r m r e s .
as4c32m16d 2 alliance memory in c . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 44 rev. 1. 1 feb . /201 3 figure 16. odt timing mode switch at exit power - down mode c k # c k t i s c k e t a o f d t a o n d o d t t a x p d t 0 t 1 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 1 e x i t i n g f r o m s l o w a c t i v e p o w e r d o w n m o d e o r p r e c h a r g e p o w e r d o w n m o d e . i n t e r n a l t e r m r e s . t i s v i l ( a c ) o d t i n t e r n a l t e r m r e s . t i s v i l ( a c ) a c t i v e & s t a n d b y m o d e t i m i n g s t o b e a p p l i e d . p o w e r d o w n m o d e t i m i n g s t o b e a p p l i e d . t i s v i h ( a c ) a c t i v e & s t a n d b y m o d e t i m i n g s t o b e a p p l i e d . t a o n p d m a x t i s v i h ( a c ) p o w e r d o w n m o d e t i m i n g s t o b e a p p l i e d . o d t o d t i n t e r n a l t e r m r e s . i n t e r n a l t e r m r e s . r t t t a o f p d m a x v i h ( a c ) r t t r t t r t t
as4c32m16d 2 alliance memory in c . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 45 rev. 1. 1 feb . /201 3 figure 17. bank activate command cycle (t rcd =3, al=2, t rp =3, t rrd =2, t ccd =2) figure 18.1. posted cas# operation: al=2 read followed by a write to the same bank c k # t 0 t 1 t 2 t 3 t n t n + 1 t n + 2 i n t e r n a l r a s # - c a s # d e l a y ( > = t r c d m i n ) c a s # - c a s # d e l a y t i m e ( t c c d ) t r c d = 1 r e a d b e g i n s t n + 3 b a n k a r o w a d d r . b a n k a c o l . a d d r . b a n k b r o w a d d r . b a n k b c o l . a d d r b a n k a a d d r . b a n k b a d d r . b a n k a r o w a d d r . a d d i t i v e l a t e n c y d e l a y ( a l ) b a n k a a c t i v a t e b a n k a p o s t c a s # r e a d b a n k b a c t i v a t e b a n k b p o s t c a s # r e a d b a n k a p r e c h a r g e b a n k b p r e c h a r g e b a n k a a c t i v a t e r a s # - r a s # d e l a y t i m e ( > = t r r d ) b a n k a c t i v e ( > = t r a s ) b a n k p r e c h a r g e t i m e ( > = t r p ) r a s # c y c l e t i m e ( > = t r c ) a d d r e s s c o m m a n d c k c k # c m d a l = 2 - 1 1 2 3 4 5 6 7 8 9 0 1 0 1 1 1 2 a c t i v e a - b a n k r e a d a - b a n k w r i t e a - b a n k c l = 3 w l = r l - 1 = 4 d o u t 0 d o u t 1 d o u t 2 d o u t 3 d i n 0 d i n 1 d i n 2 d i n 3 r l = a l + c l = 5 > = t r c d [ a l = 2 a n d c l = 3 , r l = ( a l + c l ) = 5 , w l = ( r l - 1 ) = 4 , b l = 4 ] d q s d q c k d q s #
as4c32m16d 2 alliance memory in c . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 46 rev. 1. 1 feb . /201 3 figure 18.2. posted cas# operation: al=0 read followed by a write to the same bank c k # c m d a l = 0 - 1 1 2 3 4 5 6 7 8 9 0 1 0 1 1 1 2 a c t i v e a - b a n k r e a d a - b a n k w r i t e a - b a n k c l = 3 w l = r l - 1 = 2 d o u t 0 d o u t 1 d o u t 2 d o u t 3 d i n 0 d i n 1 d i n 2 d i n 3 r l = a l + c l = 3 > = t r c d [ a l = 0 a n d c l = 3 , r l = ( a l + c l ) = 3 , w l = ( r l - 1 ) = 2 , b l = 4 ] d q s d q c k d q s #
as4c32m16d 2 alliance memory in c . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 47 rev. 1. 1 feb . /201 3 figure 19. data output (read) timing figure 20.1. burst read operati on: rl=5 (al=2, cl=3, bl=4) figure 20.2. burst read operation: rl=3 (al=0, cl=3, bl=8) c k # c k d q t d q s q m a x c k t c h t r p s t t r p r e d q s t c l d q s # d q s q q q t q h q t q h t d q s q m a x d q s # c k c k # d q s c m d d q s t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 p o s t e d c a s # r e a d a n o p n o p n o p n o p n o p n o p n o p n o p = < t d q s c k d o u t a 0 d o u t a 1 d o u t a 2 d o u t a 3 a l = 2 c l = 3 r l = 5 d q s # c k c k # d q s c m d d q s t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 r e a d a n o p n o p n o p n o p n o p n o p n o p n o p d o u t a 0 d o u t a 1 d o u t a 2 d o u t a 3 c l = 3 r l = 3 d q s # = < t d q s c k d o u t a 4 d o u t a 5 d o u t a 6 d o u t a 7
as4c32m16d 2 alliance memory in c . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 48 rev. 1. 1 feb . /201 3 figure 21. burst read followed by burst write: rl=5, wl= (rl - 1) =4, bl=4 figure 22. seamless burst read operation: rl=5, al=2, cl=3, bl=4 c k c k # d q s c m d d q s t 0 t 1 t n - 1 t n t n + 1 t n + 2 t n + 3 t n + 4 t n + 5 p o s t c a s # r e a d a n o p n o p p o s t c a s # w r i t e a n o p n o p n o p n o p n o p d o u t a 0 r l = 5 d q s # t r t w ( r e a d t o w r i t e t u r n a r o u n d t i m e ) w l = r l - 1 = 4 d o u t a 1 d o u t a 2 d o u t a 3 d i n a 0 d i n a 1 d i n a 2 d i n a 3 n o t e : t h e m i n i m u m t i m e f r o m t h e b u r s t r e a d c o m m a n d t o t h e b u r s t w r i t e c o m m a n d i s d e f i n e d b y a r e a d - t o - w r i t e - t u r n - a r o u n d - t i m e , w h i c h i s 4 c l o c k s i n c a s e o f b l = 4 o p e r a t i o n , 6 c l o c k s i n c a s e o f b l = 8 o p e r a t i o n . c k c k # d q s c m d d q s t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 p o s t c a s # r e a d a n o p p o s t c a s # r e a d b n o p n o p n o p n o p n o p n o p d o u t a 0 a l = 2 d q s # d o u t a 1 d o u t a 2 d o u t a 3 d o u t b 0 d o u t b 1 d o u t b 2 c l = 3 r l = 5 n o t e : t h e s e a m l e s s b u r s t r e a d o p e r a t i o n i s s u p p o r t e d b y e n a b l i n g a r e a d c o m m a n d a t e v e r y o t h e r c l o c k f o r b l = 4 o p e r a t i o n , a n d e v e r y 4 c l o c k f o r b l = 8 o p e r a t i o n . t h i s o p e r a t i o n i s a l l o w e d r e g a r d l e s s o f s a m e o r d i f f e r e n t b a n k s a s l o n g a s t h e b a n k s a r e a c t i v a t e d .
as4c32m16d 2 alliance memory in c . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 49 rev. 1. 1 feb . /201 3 figure 23. read burst interrupt timing: (cl=3, al=0, rl=3, bl=8) figure 24. data input (write) timing c k # c k c m d r e a d a n o p r e a d b n o p n o p n o p n o p n o p n o p n o p a 0 a 1 a 2 a 3 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 d q s d q s # d q s n o t e 1 : r e a d b u r s t i n t e r r u p t f u n c t i o n i s o n l y a l l o w e d o n b u r s t o f 8 . b u r s t i n t e r r u p t o f 4 i s p r o h i b i t e d . n o t e 2 : r e a d b u r s t o f 8 c a n o n l y b e i n t e r r u p t e d b y a n o t h e r r e a d c o m m a n d . r e a d b u r s t i n t e r r u p t i o n b y w r i t e c o m m a n d o r p r e c h a r g e c o m m a n d i s p r o h i b i t e d . n o t e 3 : r e a d b u r s t i n t e r r u p t m u s t o c c u r e x a c t l y t w o c l o c k s a f t e r p r e v i o u s r e a d c o m m a n d . a n y o t h e r r e a d b u r s t i n t e r r u p t t i m i n g s a r e p r o h i b i t e d . n o t e 4 : r e a d b u r s t i n t e r r u p t i o n i s a l l o w e d t o a n y b a n k i n s i d e d r a m . n o t e 5 : r e a d b u r s t w i t h a u t o p r e c h a r g e e n a b l e d i s n o t a l l o w e d t o i n t e r r u p t . n o t e 6 : r e a d b u r s t i n t e r r u p t i o n i s a l l o w e d b y a n o t h e r r e a d w i t h a u t o p r e c h a r g e c o m m a n d . n o t e 7 : a l l c o m m a n d t i m i n g s a r e r e f e r e n c e d t o b u r s t l e n g t h s e t i n t h e m o d e r e g i s t e r . t h e y a r e n o t r e f e r e n c e d t o a c t u a l b u r s t . f o r e x a m p l e , m i n i m u m r e a d t o p r e c h a r g e t i m i n g i s a l + b l / 2 w h e r e b l i s t h e b u r s t l e n g t h s e t i n t h e m o d e r e g i s t e r a n d n o t t h e a c t u a l b u r s t ( w h i c h i s s h o r t e r b e c a u s e o f i n t e r r u p t ) . d q s # d q d q s t d q s h t w p r e d q s d m t d q s l t w p s l v i l ( a c ) v i h ( a c ) d d v i l ( d c ) v i h ( d c ) d d d m i n d m i n d q s # d m i n v i h ( a c ) v i l ( a c ) d m i n v i h ( d c ) v i l ( d c ) t d s t d s t d h t d h
as4c32m16d 2 alliance memory in c . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 50 rev. 1. 1 feb . /201 3 figure 25.1. burst write operation: rl=5 (al=2, cl=3), wl=4, bl=4 figure 25.2. burst write operation: rl=3 (al=0, cl=3), wl=2, bl=4 c k # c k t d q s s c m d c a s e 1 : w i t h t d q s s ( m a x ) > = t w r t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t n p o s t e d c a s # w r i t e a n o p n o p n o p n o p n o p n o p n o p p r e c h a r g e t d s s t d q s s t d s s c o m p l e t i o n o f t h e b u r s t w r i t e w l = r l - 1 = 4 d n a 0 d n a 1 d n a 2 d n a 3 d q s d q s # > = t w r w l = r l - 1 = 4 d n a 0 d n a 1 d n a 2 d n a 3 d q s d q s # t d q s s t d s h t d q s s t d s h c a s e 2 : w i t h t d q s s ( m i n ) d q s d q s c k # c k < = t d q s s c m d > = t w r t 0 t 1 t 2 t 3 t 4 t 5 t m t m + 1 t n w r i t e a n o p n o p n o p n o p n o p p r e c h a r g e n o p b a n k a a c t i v a t e c o m p l e t i o n o f t h e b u r s t w r i t e w l = r l - 1 = 2 d n a 0 d n a 1 d n a 2 d n a 3 d q s d q s # d q s > = t r p
as4c32m16d 2 alliance memory in c . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 51 rev. 1. 1 feb . /201 3 figure 26. burst write fol lowed by burst read: rl=5 (al=2, cl=3, wl=4, t wtr =2, bl=4) figure 27. seamless burst write operation rl=5, wl=4, bl=4 c k # c k c k e t 0 t 1 t 4 t 5 t 6 t 7 t 8 t 9 t 2 t 3 n o p n o p n o p n o p p o s t c a s # r e a d a n o p n o p n o p n o p d q s a l = 2 d q s # w l = r l - 1 = 4 d q s # d q s c l = 3 r l = 5 > = t w t r d n a 0 d n a 1 d n a 2 d n a 3 d o u t a 0 d q n o t e : t h e m i n i m u m n u m b e r o f c l o c k f r o m t h e b u r s t w r i t e c o m m a n d t o t h e b u r s t r e a d c o m m a n d i s [ c l - 1 + b l / 2 + t w t r ] . t h i s t w t r i s n o t a w r i t e r e c o v e r y t i m e ( t w r ) b u t t h e t i m e r e q u i r e d t o t r a n s f e r t h e 4 b i t w r i t e d a t a f r o m t h e i n p u t b u f f e r i n t o s e n s e a m p l i f i e r s i n t h e a r r a y . t w t r i s d e f i n e d i n t h e t i m i n g p a r a m e t e r t a b l e o f t h i s s t a n d a r d . w r i t e t o r e a d = c l - 1 + b l / 2 + t w t r c k # c k c m d t 0 t 1 t 4 t 5 t 6 t 7 t 8 t 2 t 3 p o s t c a s # w r i t e a n o p p o s t c a s # w r i t e b n o p n o p n o p n o p n o p n o p d q s d q s # w l = r l - 1 = 4 d q s # d q s d n a 0 d n a 1 d n a 2 d n a 3 d q d n b 0 d n b 1 d n b 2 d n b 3 n o t e : t h e s e a m l e s s b u r s t w r i t e o p e r a t i o n i s s u p p o r t e d b y e n a b l i n g a w r i t e c o m m a n d e v e r y o t h e r c l o c k f o r b l = 4 o p e r a t i o n , e v e r y f o u r c l o c k s f o r b l = 8 o p e r a t i o n . t h i s o p e r a t i o n i s a l l o w e d r e g a r d l e s s o f s a m e o r d i f f e r e n t b a n k s a s l o n g a s t h e b a n k s a r e a c t i v a t e d .
as4c32m16d 2 alliance memory in c . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 52 rev. 1. 1 feb . /201 3 figure 28. write burst interrupt timing: (cl=3, al=0, rl=3, wl=2, bl= 8) c k # c k c m d n o p w r i t e a n o p w r i t e b n o p n o p n o p n o p n o p n o p a 0 a 1 a 2 a 3 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 d q s d q s # d q s n o t e 1 : w r i t e b u r s t i n t e r r u p t f u n c t i o n i s o n l y a l l o w e d o n b u r s t o f 8 . b u r s t i n t e r r u p t o f 4 i s p r o h i b i t e d . n o t e 2 : w r i t e b u r s t o f 8 c a n o n l y b e i n t e r r u p t e d b y a n o t h e r w r i t e c o m m a n d . w r i t e b u r s t i n t e r r u p t i o n b y r e a d c o m m a n d o r p r e c h a r g e c o m m a n d i s p r o h i b i t e d . n o t e 3 : w r i t e b u r s t i n t e r r u p t m u s t o c c u r e x a c t l y t w o c l o c k s a f t e r p r e v i o u s w r i t e c o m m a n d . a n y o t h e r w r i t e b u r s t i n t e r r u p t t i m i n g s a r e p r o h i b i t e d . n o t e 4 : w r i t e b u r s t i n t e r r u p t i o n i s a l l o w e d t o a n y b a n k i n s i d e d r a m . n o t e 5 : w r i t e b u r s t w i t h a u t o p r e c h a r g e e n a b l e d i s n o t a l l o w e d t o i n t e r r u p t . n o t e 6 : w r i t e b u r s t i n t e r r u p t i o n i s a l l o w e d b y a n o t h e r w r i t e w i t h a u t o p r e c h a r g e c o m m a n d . n o t e 7 : a l l c o m m a n d t i m i n g s a r e r e f e r e n c e d t o b u r s t l e n g t h s e t i n t h e m o d e r e g i s t e r . t h e y a r e n o t r e f e r e n c e d t o a c t u a l b u r s t . f o r e x a m p l e , m i n i m u m w r i t e t o p r e c h a r g e t i m i n g i s w l + b l / 2 + t w r w h e r e t w r s t a r t s w i t h t h e r i s i n g c l o c k a f t e r t h e u n i n t e r r u p t e d b u r s t e n d a n d n o t f r o m t h e e n d o f a c t u a l b u r s t e n d .
as4c32m16d 2 alliance memory in c . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 53 rev. 1. 1 feb . /201 3 figure 29. write data mask d q d q s d m d q s # t d s v i h ( a c ) v i h ( d c ) v i l ( a c ) v i l ( d c ) t d h t d s v i h ( a c ) v i h ( d c ) v i l ( a c ) v i l ( d c ) t d h c k # c k c o m m a n d d q s d q s # d q w r i t e t w r w l t d q s s t d q s s d m c a s e 2 : m a x t d q s s d q s d q s # d q d m c a s e 1 : m i n t d q s s d a t a m a s k f u n c t i o n , w l = 3 , a l = 0 , b l = 4 s h o w n d a t a m a s k t i m i n g
as4c32m16d 2 alliance memory in c . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 54 rev. 1. 1 feb . /201 3 figure 30.1. burst read operation followed by precharge: (rl=4, al=1, cl=3, bl=4, t rtp # 2 clocks) figure 30.2.burst read operation followed by precharge: (rl=4, al=1, cl=3, bl=8, t rtp # 2 clocks) c k # c k c m d t 0 t 1 t 4 t 5 t 6 t 7 t 8 t 2 t 3 p o s t c a s # r e a d a n o p n o p p r e c h a r g e n o p n o p n o p b a n k a a c t i v e n o p d q s d q s # a l + b l ' / 2 c l k s d o u t a 0 d o u t a 1 d o u t a 2 d o u t a 3 d q > = t r p a l = 1 c l = 3 r l = 4 > = t r a s > = t r t p c l = 3 c k # c k c m d t 0 t 1 t 4 t 5 t 6 t 7 t 8 t 2 t 3 p o s t c a s # r e a d a n o p n o p n o p n o p p r e c h a r g e a n o p n o p n o p d q s d q s # r l = 4 d o u t a 0 d o u t a 1 d o u t a 2 d o u t a 3 d q ' s a l + b l / 2 c l k s c l = 3 a l = 1 f i r s t 4 - b i t p r e f e t c h > = t r t p s e c o n d 4 - b i t p r e f e t c h d o u t a 4 d o u t a 5 d o u t a 6 d o u t a 8
as4c32m16d 2 alliance memory in c . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 55 rev. 1. 1 feb . /201 3 figure 30.3. burst read operation followed by precharge: (rl=5, al=2, cl=3, bl =4, t rtp # 2 clocks) figure 30.4. burst read operation followed by precharge: (rl=6, al=2, cl=4, bl=4, t rtp # 2 clocks) c k # c k c m d t 0 t 1 t 4 t 5 t 6 t 7 t 8 t 2 t 3 p o s t c a s # r e a d a n o p n o p n o p p r e c h a r g e a n o p n o p b a n k a a c t i v a t e n o p d q s d q s # r l = 5 d o u t a 0 d o u t a 1 d o u t a 2 d o u t a 3 d q ' s a l + b l / 2 c l k s c l = 3 a l = 2 > = t r a s > = t r p c l = 3 > = t r t p c k # c k c m d t 0 t 1 t 4 t 5 t 6 t 7 t 8 t 2 t 3 p o s t c a s # r e a d a n o p n o p n o p p r e c h a r g e a n o p n o p b a n k a a c t i v a t e n o p d q s d q s # r l = 6 d o u t a 0 d o u t a 1 d o u t a 2 d o u t a 3 d q ' s a l + b l / 2 c l k s c l = 4 a l = 2 > = t r a s > = t r p c l = 4 > = t r t p
as4c32m16d 2 alliance memory in c . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 56 rev. 1. 1 feb . /201 3 figure 30.5. burst read operation followed by precharge: (rl=4, al=0, c l=4, bl=8, t rtp >2 clocks) figure 31.1. burst write operation followed by precharge: wl= (rl - 1) =3 c k # c k c m d t 0 t 1 t 4 t 5 t 6 t 7 t 8 t 2 t 3 p o s t c a s # r e a d a n o p n o p n o p n o p p r e c h a r g e a n o p n o p b a n k a a c t i v a t e d q s d q s # r l = 4 d o u t a 0 d o u t a 1 d o u t a 2 d o u t a 3 d q ' s a l + 2 + m a x ( t r t p , 2 t c k ) * c l = 4 a l = 0 f i r s t 4 - b i t p r e f e t c h > = t r t p s e c o n d 4 - b i t p r e f e t c h d o u t a 4 d o u t a 5 d o u t a 6 d o u t a 8 > = t r p > = t r a s * : r o u n d e d t o n e x t i n t e g e r . c k # c k c m d t 0 t 1 t 4 t 5 t 6 t 7 t 8 t 2 t 3 p o s t c a s # w r i t e a n o p n o p n o p n o p n o p n o p n o p p r e c h a r g e a d q s d q s # d n a 0 d n a 1 d n a 2 d n a 3 d q ' s > = t w r w l = 3 c o m p l e t i o n o f t h e b u r s t w r i t e
as4c32m16d 2 alliance memory in c . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 57 rev. 1. 1 feb . /201 3 figure 31.2. burst write followed by precharge: wl= (rl - 1) =4 figure 32.1. burst read operation with auto precharge: (rl=4,al=1, cl=3, bl=8, t rtp # 2 clocks) c k # c k c m d t 0 t 1 t 4 t 5 t 6 t 7 t 9 t 2 t 3 p o s t c a s # w r i t e a n o p n o p n o p n o p n o p n o p n o p p r e c h a r g e a d q s d q s # d n a 0 d n a 1 d n a 2 d n a 3 d q ' s > = t w r w l = 4 c o m p l e t i o n o f t h e b u r s t w r i t e c k # c k c m d t 0 t 1 t 4 t 5 t 6 t 7 t 8 t 2 t 3 p o s t c a s # r e a d a n o p n o p n o p n o p n o p n o p n o p b a n k a a c t i v a t e d q s d q s # r l = 4 d o u t a 0 d o u t a 1 d o u t a 2 d o u t a 3 d q ' s a l + b l / 2 c l k s c l = 3 a l = 1 a u t o p r e c h a r g e > = t r t p s e c o n d 4 - b i t p r e f e t c h d o u t a 4 d o u t a 5 d o u t a 6 d o u t a 8 > = t r p t r t p p r e c h a r g e b e g i n s h e r e f i r s t 4 - b i t p r e f e t c h
as4c32m16d 2 alliance memory in c . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 58 rev. 1. 1 feb . /201 3 figure 32.2. burst read operation with auto precharge: (rl=4, al=1, cl=3, bl=4, t rtp >2 clocks) figure 32.3. burst read operation with auto precharge followed by activation t o the same bank (t rc limit): rl=5(al=2, cl=3, internal t rcd =3, bl=4, t rtp # 2 clocks) c k # c k c m d t 0 t 1 t 4 t 5 t 6 t 7 t 8 t 2 t 3 p o s t c a s # r e a d a n o p n o p n o p n o p n o p n o p b a n k a a c t i v a t e n o p d q s d q s # d o u t a 0 d o u t a 1 d o u t a 2 d o u t a 3 d q ' s c l = 3 a u t o p r e c h a r g e > = a l + t r t p + t r p a l = 1 r l = 4 t r t p t r p f i r s t 4 - b i t p r e f e t c h p r e c h a r g e b e g i n s h e r e c k # c k c m d t 0 t 1 t 4 t 5 t 6 t 7 t 8 t 2 t 3 p o s t c a s # r e a d a n o p n o p n o p n o p n o p n o p n o p b a n k a a c t i v a t e d q s d q s # d o u t a 0 d o u t a 1 d o u t a 2 d o u t a 3 d q ' s c l = 3 > = t r a s ( m i n ) a l = 2 r l = 5 > = t r c c l = 3 a 1 0 = 1 a u t o p r e c h a r g e b e g i n s > = t r p
as4c32m16d 2 alliance memory in c . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 59 rev. 1. 1 feb . /201 3 figure 32.4. burst read operation with auto precharge followed by an activation to the same bank (t rp limit): (rl=5 (al=2, cl=3, intern al t rcd =3, bl=4, t rtp # 2 clocks) figure 33.1. burst write with auto - precharge (t rc limit): wl=2, wr=2, bl=4, t rp =3 c k # c k c m d t 0 t 1 t 4 t 5 t 6 t 7 t 8 t 2 t 3 p o s t c a s # r e a d a n o p n o p n o p n o p n o p n o p b a n k a a c t i v a t e n o p d q s d q s # d o u t a 0 d o u t a 1 d o u t a 2 d o u t a 3 d q ' s c l = 3 > = t r a s ( m i n ) a l = 2 r l = 5 > = t r c c l = 3 a 1 0 = 1 a u t o p r e c h a r g e b e g i n s > = t r p c k # c k c m d t 0 t 1 t 4 t 5 t 6 t 7 t m t 2 t 3 p o s t c a s # w r a b a n k a n o p n o p n o p n o p n o p n o p n o p b a n k a a c t i v e d q s d q s # d n a 0 d n a 1 d n a 2 d n a 3 d q ' s a u t o p r e c h a r g e b e g i n s w l = r l - 1 = 2 c o m p l e t i o n o f t h e b u r s t w r i t e a 1 0 = 1 > = w r > = t r p > = t r c
as4c32m16d 2 alliance memory in c . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 60 rev. 1. 1 feb . /201 3 figure 33.2. burst write with auto - precharge (wr+t rp ): wl=4, wr=2, bl=4 , t rp =3 figure 34. refresh command c k # c k c m d t 0 t 3 t 6 t 7 t 8 t 9 t 1 2 t 4 t 5 p o s t c a s # w r a b a n k a n o p n o p n o p n o p n o p n o p n o p b a n k a a c t i v e d q s d q s # d n a 0 d n a 1 d n a 2 d n a 3 d q ' s a u t o p r e c h a r g e b e g i n s w l = r l - 1 = 4 c o m p l e t i o n o f t h e b u r s t w r i t e a 1 0 = 1 > = w r > = t r p > = t r c c k # c k c k e t 0 t 1 t m t n t n + 1 t 2 t 3 p r e c h a r g e n o p n o p r e f r e f n o p a n y c m d h i g h > = t r p > = t r f c > = t r f c
as4c32m16d 2 alliance memory in c . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 61 rev. 1. 1 feb . /201 3 figure 35. self refresh operation figure 36. basic power down entry and exit timing diagram c k # c k c k e t 0 t 1 t 5 t m t 2 t 3 c m d > = t x s n r t r p * t c h t c l t c k t 4 t 6 t n > = t x s r d t i s v i l ( a c ) v i h ( a c ) t i s n o p s e l f r e f r e s h o d t t a o f d t i s v i l ( a c ) t i h t i s t i h t i s t i h v i l ( d c ) v i l ( a c ) v i h ( a c ) v i h ( d c ) n o p n o p v a l i d n o t e 1 d e v i c e m u s t b e i n t h e " a l l b a n k s i d l e " s t a t e p r i o r t o e n t e r i n g s e l f r e f r e s h m o d e . n o t e 2 o d t m u s t b e t u r n e d o f f t a o f d b e f o r e e n t e r i n g s e l f r e f r e s h m o d e , a n d c a n b e t u r n e d o n a g a i n w h e n t x s r d t i m i n g i s s a t i s f i e d . n o t e 3 t x s r d i s a p p l i e d f o r r e a d o r a r e a d w i t h a u t o p r e c h a r g e c o m m a n d . t x s n r i s a p p l i e d f o r a n y c o m m a n d e x c e p t a r e a d o r a r e a d w i t h a u t o p r e c h a r g e c o m m a n d . c k # c k c o m m a n d c k e v a l i d t i h t c k e m i n t i h t i h t i h t i s t i s t i s n o p n o p n o p v a l i d v a l i d o r n o p t x p , t x a r d t x a r d s t c k e ( m i n ) e x i t p o w e r - d o w n m o d e d o n ' t c a r e e n t e r p o w e r - d o w n m o d e
as4c32m16d 2 alliance memory in c . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 62 rev. 1. 1 feb . /201 3 figure 37.1.cke intensive environment figure 37.2.cke intensive environment c k # c k e t c k e n o t e : d r a m g u a r a n t e e s a l l a c a n d d c t i m i n g & v o l t a g e s p e c i f i c a t i o n s a n d p r o p e r d l l o p e r a t i o n w i t h i n t e n s i v e c k e o p e r a t i o n c k t c k e t c k e t c k e c k # c k e t c k e n o t e : t h e p a t t e r n s h o w n a b o v e c a n r e p e a t o v e r a l o n g p e r i o d o f t i m e . w i t h t h i s p a t t e r n , d r a m g u a r a n t e e s a l l a c a n d d c t i m i n g & v o l t a g e s p e c i f i c a t i o n s a n d d l l o p e r a t i o n w i t h t e m p e r a t u r e a n d v o l t a g e d r i f t c k t c k e t c k e t c k e t x p t x p t r e f i = 3 . 9 s r e f r e f c m d
as4c32m16d 2 alliance memory in c . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 63 rev. 1. 1 feb . /201 3 figure 38. read to power - down entry c k # c m d b l = 4 t 0 t 2 t x t x + 1 t x + 2 t x + 3 t x + 4 t x + 5 t x + 6 t x + 7 t 1 t x + 8 t x + 9 r d q a l + c l r e a d o p e r a t i o n s t a r t s w i t h a r e a d c o m m a n d a n d d q s c k e c k d q s # c k e s h o u l d b e k e p t h i g h u n t i l t h e e n d o f b u r s t o p e r a t i o n t i s q q q d q c k # c m d b l = 8 t 0 t 2 t x t x + 1 t x + 2 t x + 3 t x + 4 t x + 5 t x + 6 t x + 7 t 1 t x + 8 t x + 9 r d q a l + c l d q s c k e c k d q s # c k e s h o u l d b e k e p t h i g h u n t i l t h e e n d o f b u r s t o p e r a t i o n t i s q q q d q q q q q
as4c32m16d 2 alliance memory in c . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 64 rev. 1. 1 feb . /201 3 figure 39. read with autoprecharge to power - down entry c k # c m d b l = 4 t 0 t 2 t x t x + 1 t x + 2 t x + 3 t x + 4 t x + 5 t x + 6 t x + 7 t 1 t x + 8 t x + 9 r d a q a l + c l d q s c k e c k d q s # c k e s h o u l d b e k e p t h i g h u n t i l t h e e n d o f b u r s t o p e r a t i o n t i s q q q d q c k # c m d b l = 8 t 0 t 2 t x t x + 1 t x + 2 t x + 3 t x + 4 t x + 5 t x + 6 t x + 7 t 1 t x + 8 t x + 9 r d q a l + c l d q s c k e c k d q s # c k e s h o u l d b e k e p t h i g h u n t i l t h e e n d o f b u r s t o p e r a t i o n t i s q q q d q q q q q p r e a l + b l / 2 w i t h t r t p = 7 . 5 n s & t r a s m i n s a t i s f i e d p r e s t a r t i n t e r n a l p r e c h a r g e a l + b l / 2 w i t h t r t p = 7 . 5 n s & t r a s m i n s a t i s f i e d
as4c32m16d 2 alliance memory in c . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 65 rev. 1. 1 feb . /201 3 figure 40. write to power - down entry c k # c m d b l = 4 t 0 t m t m + 1 t m + 2 t m + 3 t x t x + 1 t x + 2 t y t y + 1 t 1 t y + 2 t y + 3 w r q w l d q s c k e c k d q s # t i s q q q d q c k # c m d b l = 8 t 0 t m t m + 1 t m + 2 t m + 3 t m + 4 t m + 5 t x t x + 1 t x + 2 t 1 t x + 3 t x + 4 w r q w l d q s c k e c k d q s # q q q d q q q q q t w t r t i s t w t r
as4c32m16d 2 alliance memory in c . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 66 rev. 1. 1 feb . /201 3 figure 41. write with autoprecharge to power - down entry figure 42. refresh command to power - down entry c k # c m d b l = 4 t 0 t m t m + 1 t m + 2 t m + 3 t x t x + 1 t x + 2 t x + 3 t x + 4 t 1 t x + 5 t x + 6 w r a q w l d q s c k e c k d q s # t i s q q q d q c k # c m d b l = 8 t 0 t m t m + 1 t m + 2 t m + 3 t m + 4 t m + 5 t x t x + 1 t x + 2 t 1 t x + 3 t x + 4 w r a q w l d q s c k e c k d q s # q q q d q q q q q w r * 1 t i s p r e w r * 1 p r e s t a r t i n t e r n a l p r e c h a r g e * 1 : w r i s p r o g r a m m e d t h r o u g h m r s c k # c m d t 0 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 r e f c k e c k t i s t 1 1 c k e c a n g o t o l o w o n e c l o c k a f t e r a n a u t o - r e f r e s h c o m m a n d
as4c32m16d 2 alliance memory in c . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 67 rev. 1. 1 feb . /201 3 figure 43. active command to power - down entry figure 44. precharge/ precharge - all command to power - down entry figure 45. mrs/emrs command to power - down entry c m d t 0 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 a c t c k e t i s t 1 1 c k e c a n g o t o l o w o n e c l o c k a f t e r a n a c t i v e c o m m a n d c m d t 0 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 p r o r p r a c k e t i s t 1 1 c k e c a n g o t o l o w o n e c l o c k a f t e r a p r e c h a r g e o r p r e c h a r g e a l l c o m m a n d c m d t 0 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 m r s o r e m r s c k e t i s t 1 1 t m r d
as4c32m16d 2 alliance memory in c . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 68 rev. 1. 1 feb . /201 3 figure 46. asynchronous cke low event figure 47. clock freq uency change in precharge power down mode c k # c k c k e t c k t d e l a y c k e a s y n c h r o n o u s l y d r o p s l o w c l o c k s c a n b e t u r n e d o f f a f t e r t h i s p o i n t t i s s t a b l e c l o c k s c k # c m d t 0 t 2 t 4 t x t x + 1 t y t y + 1 t y + 2 t y + 3 t y + 4 t 1 t z f r e q u e n c y c h a n g e o c c u r s h e r e t r p c k e o d t c k n o p n o p n o p n o p d l l r e s e t n o p v a l i d 2 0 0 c l o c k s t a o f d m i n i m u m 2 c l o c k s r e q u i r e d b e f o r e c h a n g i n g f r e q u e n c y s t a b l e n e w c l o c k b e f o r e p o w e r d o w n e x i t t x p t i s t i s t i h o d t i s o f f d u r i n g d l l r e s e t
as4c32m16d 2 alliance memory in c . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 69 rev. 1. 1 feb . /201 3 figure 48. 84 - ball 8x12.5x1.2mm(max.) fbga package outline drawing information symbol dimension in inch dimension in mm min nom ma x min nom max a -- -- 0.047 -- -- 1.20 a1 0.010 -- 0.016 0.25 -- 0.40 a2 0.030 0.031 0.033 0.75 0.80 0.85 a3 0.005 0.006 0.007 0.125 0.155 0.185 d 0.311 0.315 0.319 7.9 8.0 8.1 e 0.488 0.492 0.496 12.4 12.5 12.6 d1 -- 0.252 -- -- 6.40 -- e1 -- 0.44 1 -- -- 11.2 -- f -- 0.126 -- -- 3.2 -- e -- 0.031 -- -- 0.80 -- b 0.016 0.018 0.020 0.40 0.45 0.50 d2 -- -- 0.081 -- -- 2.05 top view bottom view side view pin a1 index detail : "a"
as4c32m16d 2 alliance memory in c . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 70 rev. 1. 1 feb . /201 3

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